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PDF X28HT010 Data sheet ( Hoja de datos )
| Número de pieza | X28HT010 | |
| Descripción | (X28C010 / X28HT010) Byte Alterable EEPROM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X28HT010 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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®
Data Sheet
X28C010, X28HT010
February 12, 2007
FN8105.1
5V, Byte Alterable EEPROM
The Intersil X28C010/X28HT010 is a 128K x 8 EEPROM,
fabricated with Intersil's proprietary, high performance,
floating gate CMOS technology. Like all Intersil
programmable non-volatile memories, the
X28C010/X28HT010 is a 5V only device. The
X28C010/X28HT010 features the JEDEC approved pin out
for byte-wide memories, compatible with industry standard
EEPROMs.
The X28C010/X28HT010 supports a 256-byte page write
operation, effectively providing a 19µs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C010/X28HT010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion of a
write cycle. In addition, the X28C010/X28HT010 supports
Software Data Protection option.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
www.DataSheet4U.com
Features
• Access time: 120ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or VPP control
circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
- Active: 50mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write™ cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• X28HT010 is fuly functional @ +175°C
Pinouts
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
CERDIP
Flat Pack
SOIC (R)
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 X28C010 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PGA
15I/O0 17I/O2 19I/O3 21I/O5 22I/O6
A1 A0 I/O1 VSS I/O4 I/O7 CE
13 14 16 18 20 23 24
12A2 11A3
25A10
OE
26
10A4
9A5
X28C010
(Bottom View)
27A11
A
28
9
8A6 7A7
29A8
A
30
13
A12 A15 NC VCC NC NC A 14
6 5 2 36 34 32 31
4A16
NC
3
NC WE NC
1 35 33
EXTENDED LCC
4 3 2 32 31 30
A7 5
A6 6
A5 7
1
29 A14
28 A13
27 A8
A4
A3
A2
8
9
10
X28C010
(Top View)
26
25
24
A9
A11
OE
A1 11
23 A10
A0 12
22 CE
I/O 0 13
21 I/O7
14 15 16 17 18 19 20
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Write Data
Writes
Complete?
Yes
Save Last Data
and Address
No
X28C010, X28HT010
DATA Polling can effectively halve the time for writing to the
X28C010/X28HT010. The timing diagram in Figure 2
illustrates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
Read Last
Address
IO7
Compare?
Yes
X28C010
Ready
No
FIGURE 3. DATA POLLING SOFTWARE FLOW
The Toggle Bit I/O6
Last
WE Write
CE
OE
I/O6
VOH
*
VOL
HIGH Z
*
* Beginning and ending state of I/O6 will vary
FIGURE 4. TOGGLE BIT BUS SEQUENCE
X28C010
Ready
5 FN8105.1
February 12, 2007
5 Page 
X28C010, X28HT010
Endurance and Data Retention
PARAMETER
Endurance
Endurance
Data Retention
MIN
10,000
100,000
100
MAX
UNIT
Cycles per byte
Cycles per page
Years
A.C. Conditions of Test
Input pulse levels
Input rise and fall times
Input and output timing levels
0V to 3V
10ns
1.5V
Mode Selection
CE OE WE
MODE
L LH
Read
LHL
Write
H X X Standby and
Write Inhibit
X L X Write Inhibit
X X H Write Inhibit
I/O
DOUT
DIN
High Z
—
—
Equivalent A.C. Load Circuit
POWER
Active
Active
Standby
—
—
Symbol Table
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5V
1.92kΩ
Output
1.37kΩ
100pF
AC Electrical Specifications Over the recommended operating conditions, unless otherwise specified.
X28C010-12
X28C010-15
X28C010-20,
X28HT010W
SYMBOL
PARAMETER
MIN MAX MIN MAX MIN MAX
READ CYCLE LIMITS
tRC Read cycle time
tCE Chip enable access time
tAA Address access time
tOE Output enable access time
tLZ (Note 4) CE LOW to active output
tOLZ (Note 4) OE LOW to active output
tHZ (Note 4) CE HIGH to high Z output
tOHZ (Note 4) OE HIGH to high Z output
tOH Output hold from address change
120 150 200
120 150 200
120 150 200
50 50 50
000
000
50 50 50
50 50 50
000
X28C010-25
MIN MAX
UNIT
250 ns
250 ns
250 ns
50 ns
0 ns
0 ns
50 ns
50 ns
0 ns
11 FN8105.1
February 12, 2007
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet X28HT010.PDF ] | |
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