DataSheet.es X1288 Hoja de datos PDF



PDF X1288 Datasheet ( Hoja de datos )

Número de pieza X1288
Descripción RTC Real Time Clock/Calendar/CPU Supervisor
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo
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X1288 datasheet

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X1288 pdf
X1288
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10) VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC
(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1) Output Capacitance (SDA, PHZ/IRQ, RESET) 10 pF
CIN(1) Input Capacitance (SCL)
10 pF
VOUT = 0V
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard Output Load
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
SDA
1533
For VOL= 0.4V
and IOL = 3 mA
100pF
5.0V
PHZ/IRQ
1316
806
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VCC = 5.0V
5 FN8102.3
April 14, 2006

5 Page

X1288 arduino
X1288
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC reg-
isters. To avoid changing the current time by an uncom-
pleted write operation, the current time value is loaded
into a separate buffer at the falling edge of the clock on
the ACK bit before the RTC data input bytes, the clock
continues to run. The new serial input data replaces the
values in the buffer. This new RTC value is loaded back
into the RTC Register by a stop bit at the end of a valid
write sequence. An invalid write operation aborts the time
update procedure and the contents of the buffer are dis-
carded. After a valid write operation the RTC will reflect
the newly loaded data beginning with the SSEC register
reset to “0” at the next sub-second update after the stop
bit is written. The 1Hz frequency output from the
PHZ/IRQ pin will be reset to restart after the stop bit is
written. The RTC continues to update the time while an
RTC register write is in progress and the RTC continues
to run during any nonvolatile write sequences. A single
byte may be written to the RTC without affecting the
other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC performance
will also be dependent upon temperature. The frequency
deviation of the crystal is a function of the turnover
temperature of the crystal from the crystal’s nominal
frequency. For example, a >20ppm frequency deviation
translates into an accuracy of >1 minute per month.
these parameters are available from the crystal
manufacturer. Intersil’s RTC family provides on-chip
crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116 ppm
to –37 ppm when using a 12.5 pF load crystal. For more
detail information see the Application section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses from
0000h to 003Fh. The defined addresses are described in
the Table 1. Writing to and reading from the undefined
addresses are not recommended.
CCR Access
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address in
the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be set
using a two step process (See section “Writing to the
Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 supports a single byte read or
write only. Continued reads or writes from this section
terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read. The
read instruction latches all Clock registers into a buffer,
so an update of the clock does not change the time being
read. A sequential read of the CCR will not result in the
output of data from the memory array. At the end of a
read, the master supplies a stop condition to end the
operation and free the bus. After a read of the CCR, the
address remains at the previous address +1 so the user
can execute a current address read of the CCR and con-
tinue reading the next Register.
10 FN8102.3
April 14, 2006

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