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PDF X1288 Datasheet ( Hoja de datos )

Número de pieza X1288
Descripción RTC Real Time Clock/Calendar/CPU Supervisor
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo

Total 27 Páginas
		
X1288 Hoja de datos, Descripción, Manual
®
Data Sheet
April 14, 2006
X1288
FN8102.3
2-WireRTC Real Time
Clock/Calendar/CPU Supervisor with
EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, Seconds and
Hundredths of a Second
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital-frequency adjustment setting to
±30ppm
• CPU Supervisor Functions
— Power-on Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 32K x 8 Bits of EEPROM
www.DataSheet4U.com — 128-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
—Data Retention: 100 years
—Endurance: 100,000 cycles per byte
BLOCK DIAGRAM
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 16-Lead SOIC and 14-Lead TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
OSC
Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
256K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
I2C is a trademark of Philips. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page

X1288 pdf
X1288
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10) VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC
(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1) Output Capacitance (SDA, PHZ/IRQ, RESET) 10 pF
CIN(1) Input Capacitance (SCL)
10 pF
VOUT = 0V
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard Output Load
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
SDA
1533
For VOL= 0.4V
and IOL = 3 mA
100pF
5.0V
PHZ/IRQ
1316
806
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VCC = 5.0V
5 FN8102.3
April 14, 2006

5 Page

X1288 arduino
X1288
Table 1. Clock/Control Memory Map
Addr. Type
003F Status
0037
0036
RTC
(SRAM)
0035
0034
0033
0032
0031
0030
0013 Control (EE-
0012 PROM)
0011
0010
000F Alarm1
000E (EEPROM)
000D
000C
000B
000A
0009
0008
0007 Alarm0
(EEPROM)
0006
0005
0004
0003
0002
0001
0000
Reg
Name
SR
SSEC
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
BL
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
7
BAT
SS23
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
Bit
0
6 5 4 3 2 1 (optional)
AL1 AL0
0
0
RWEL
WEL
RTCF
SS22
SS21
SS20
SS13
SS12
SS11
SS10
0 0 0 0 DY2 DY1 DY0
Y22 Y21 Y20 Y13 Y12 Y11 Y10
0 0 G20 G13 G12 G11 G10
0 D21 D20 D13 D12 D11 D10
0 H21 H20 H13 H12 H11 H10
M22 M21 M20 M13 M12 M11 M10
S22 S21 S20 S13 S12 S11 S10
00
0
0
DTR2
DTR1
DTR0
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
AL1E
AL0E
FO1
FO0 Read Only Read Only Read Only
BP1 BP0 WD1 WD0 Read Only Read Only Read Only
Read-only - Default = 20h
0 0 0 0 DY2 DY1 DY0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0 0 A1G20 A1G13 A1G12 A1G11 A1G10
0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10
0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10
A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10
A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10
Read-only - Default = 20h
Range
0-99
0-6
0-99
1-12
1-31
0-23
0-59
0-59
20
0-6
1-12
1-31
0-23
0-59
0-59
20
0 0 0 0 DY2 DY1
Unused - Default = RTC Year value (No EEPROM) – Future expansion
0 0 A0G20 A0G13 A0G12 A0G11
0 A0D21 A0D20 A0D13 A0D12 A0D11
0 A0H21 A0H20 A0H13 A0H12 A0H11
A0M22 A0M21 A0M20 A0M13 A0M12 A0M11
A0S22 A0S21 A0S20 A0S13 A0S12 A0S11
DY0
A0G10
A0D10
A0H10
A0M10
A0S10
0-6
1-12
1-31
0-23
0-59
0-59
01h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
00h
18h
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1288 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SSEC, SC, MN, HR, DT,
MO, YR)
These registers depict BCD representations of the
time. As such, SSEC (1/100 Second) range from 00 to
99, SC (Seconds) and MN (Minutes) range from 00 to
59, HR (Hour) is 1 to 12 with an AM or PM indicator
11 FN8102.3
April 14, 2006

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