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PDF X1228 Datasheet ( Hoja de datos )

Número de pieza X1228
Descripción Real Time Clock/Calendar/CPU Supervisor
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo
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X1228 datasheet

1 Page

X1228 pdf
X1228
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10) VSDA = GND or VCC, VSCL = GND or VCC, VRESET = VCC or GND
(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1)
CIN(1)
Output Capacitance (SDA, PHZ/IRQ, RESET)
Input Capacitance (SCL)
10 pF
10 pF
VOUT = 0V
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard Output Load
Figure 18. Standard Output Load for testing the device with VCC = 5.0V
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
SDA
1533Ω
For VOL= 0.4V
and IOL = 3 mA
100pF
5.0V
PHZ/IRQ
1316Ω
806Ω
100pF
5 FN8100.4
May 18, 2006

5 Page

X1228 arduino
X1228
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24 hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and Real Time Registers. For
example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
003F Status
SR
0037 RTC Y2K
0036 (SRAM) DW
0035 YR
0034 MO
0033 DT
0032 HR
0031 MN
0030 SC
0013 Control DTR
0012 (EEPROM) ATR
0011 INT
0010 BL
7
BAT
0
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
6
AL1
0
0
Y22
0
0
0
M22
S22
0
0
AL1E
BP1
5
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
BP0
4
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
FO1
WD1
Bit
3
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
FO0
WD0
2
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
x
0
1
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
x
0
0 (optional)
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
x
0
Range
19/20
0-6
0-99
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
18h
11 FN8100.4
May 18, 2006

11 Page





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