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PDF X1227 Datasheet ( Hoja de datos )

Número de pieza X1227
Descripción RTC Real TimeClock/Calendar/ CPU Supervisor
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo

Total 28 Páginas
		
X1227 Hoja de datos, Descripción, Manual
® NOT RDENaSCtEaEOWESMDhIMSEeELeS1NtIG2D0NE2SD7 FOR
May 8, 2006
X1227
FN8099.2
2-WireRTC Real TimeClock/Calendar/
CPU Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks Time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal Feedback Resistor and Compensation
Capacitors
— 64 Position Digitally Controlled Trim Capacitor
— 6 Digital Frequency Adjustment Settings to ±30ppm
• CPU Supervisor Functions
— Power-On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
— 8 Modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
www.DataSheet4U.com — Data Retention: 100 Years
— Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I2C*
— 400kHz Data Transfer Rate
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 8 Ld SOIC and 8 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
DESCRIPTION
The X1227 device is a Real Time Clock with
clock/calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
BLOCK DIAGRAM
OSC
Compensation
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Battery
Switch
Circuitry
VCC
VBACK
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
*I2C is a Trademark of Philips. All other trademarks mentioned are the property of their respective owners.

1 page

X1227 pdf
X1227
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10)VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC
(11)IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15)Typical values are for TA = 25°C
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1)
CIN(1)
Output Capacitance (SDA, RESET)
Input Capacitance (SCL)
10 pF
10 pF
VOUT = 0V
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard Output Load
Figure 1. Standard Output Load for testing the device with VCC = 5.0V
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
SDA
1533Ω
For VOL= 0.4V
and IOL = 3 mA
100pF
5 FN8099.2
May 8, 2006

5 Page

X1227 arduino
X1227
reads or writes, once reaching the end of a section, will
wrap around to the start of the section. A read or write
can begin at any address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
– *n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Type
Status
RTC (SRAM)
Control
(EEPROM)
Alarm1
(EEPROM)
Alarm0
(EEPROM)
Reg
Name
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
BL
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
7
BAT
0
0
Y23
0
0
MIL
0
0
0
0
BP2
0
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
0
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
Bit
65
4
3 21
AL1 AL0
0
0 RWEL WEL
0
Y2K21
Y2K20
Y2K13
0
0
00
0
0 DY2 DY1
Y22 Y21
Y20
Y13 Y12 Y11
0 0 G20 G13 G12 G11
0 D21 D20
D13 D12 D11
0 H21 H20
H13 H12 H11
M22 M21
M20
M13 M12 M11
S22 S21
S20
S13 S12 S11
00
0
0 DTR2 DTR1
0
ATR5
ATR4
ATR3
ATR2 ATR1
Unused
BP1 BP0 WD1 WD0 0 0
0 A1Y2K21 A1Y2K20 A1Y2K13
0
0
00
0
0 DY2 DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0
0
A1G20
A1G13 A1G12 A1G11
0
A1D21
A1D20
A1D13 A1D12 A1D11
0
A1H21
A1H20
A1H13
A1H12 A1H11
A1M22 A1M21
A1M20
A1M13 A1M12 A1M11
A1S22 A1S21
A1S20
A1S13
A1S12 A1S11
0 A0Y2K21 A0Y2K20 A0Y2K13
0
0
00
0
0 DY2 DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0
0
A0G20
A0G13 A0G12 A0G11
0
A0D21
A0D20
A0D13 A0D12 A0D11
0
A0H21
A0H20
A0H13
A0H12 A0H11
A0M22 A0M21
A0M20
A0M13 A0M12 A0M11
A0S22 A0S21
A0S20
A0S13
A0S12 A0S11
0 (optional)
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
0
A1Y2K10
DY0
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
A0G10
A0D10
A0H10
A0M10
A0S10
Range
19/20
0-6
0-99
1-12
1-31
0-23
0-59
0-59
19/20
0-6
1-12
1-31
0-23
0-59
0-59
19/20
0-6
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
18h
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
11 FN8099.2
May 8, 2006

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