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PDF EL5525 Data sheet ( Hoja de datos )
| Número de pieza | EL5525 | |
| Descripción | 18-Channel TFT-LCD Reference Voltage Generator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
PRELIMINARY
Data Sheet
August 1, 2005
EL5525
FN7393.1
18-Channel TFT-LCD Reference Voltage
Generator
The EL5525 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the serial interface. A serial out pin enables
daisy chaining of multiple devices.
A number of the EL5525 can be stacked for applications
requiring more than 18 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
The EL5525 has 18 outputs and comes in a 38-pin HTSSOP
package. It is specified for operation over the full -40°C to
+85°C temperature range.
Ordering Information
www.DataSheet4U.com
PART
NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL5525IRE
38-Pin HTSSOP
-
MDP0048
EL5525IRE-T7 38-Pin HTSSOP
7”
MDP0048
EL5525IRE-T13 38-Pin HTSSOP
13”
MDP0048
EL5525IREZ
(See Note)
38-Pin HTSSOP
(Pb-Free)
-
MDP0048
EL5525IREZ-T7 38-Pin HTSSOP
(See Note)
(Pb-Free)
7”
MDP0048
EL5525IREZ-T13 38-Pin HTSSOP
(See Note)
(Pb-Free)
13”
MDP0048
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• 18-channel reference outputs
• Accuracy of ±0.1%
• Supply voltage of 4.5V to 16.5V
• Digital supply 3.3V to 5V
• Low supply current of 15mA
• Rail-to-rail capability
• Internal thermal protection
• Pb-Free plus anneal available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Reference voltage generators
Pinout
EL5525
(38-PIN HTSSOP)
TOP VIEW
ENA 1
38 OUTA
SDI 2
37 OUTB
SCLK 3
36 OUTC
SDO 4
35 GND
EXT_OSC 5
34 OUTD
VS 6
33 OUTE
VSD 7
32 OUTF
NC 8
31 OUTG
NC 9
OSC_SELECT 10
VS 11
THERMAL
PAD
30 OUTH
29 OUTI
28 GND
REFH 12
27 OUTJ
REFL 13
26 OUTK
GND 14
25 OUTL
CAP 15
24 GND
VS 16
23 OUTM
NC 17
22 OUTN
OUTR 18
21 OUTO
OUTQ 19
20 OUTP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
EL5525
General Description
The EL5525 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5525,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5525. As all of the output
buffers are identical, it is also possible to use the EL5525 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
Digital Interface
The EL5525 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5525 can support
the clock rate up to 5MHz.
Serial Interface
The EL5525 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB
(bit 15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
To facilitate the system designs that use multiple EL5525
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
To control the multiple EL5525 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
together, connect the SDO pin to the SDI pin on the next
Serial Timing Diagram
ENA
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to the Control
Bits Logic Table)
• Bit 15 is always set to a zero
• Bits 14 through 10 select the channel to be written to, these
are binary coded with channel A = 0, and channel R = 17
• The 10-bit data is on bits 9 through 0. Some examples of
data words are shown in the table of Serial Programming
Examples
TABLE 1. CONTROL BITS LOGIC TABLE
BIT NAME
DESCRIPTION
B15 Test Always 0
B14 A4 Channel Address
B13 A3 Channel Address
B12 A2 Channel Address
B11 A1 Channel Address
B10 A0 Channel Address
B9 D9 Data
B8 D8 Data
B7 D7 Data
B6 D6 Data
B5 D5 Data
B4 D4 Data
B3 D3 Data
B2 D2 Data
B1 D1 Data
B0 D0 Data
tHE tSE
T
tr
tf tHE
tSE
SCLK
tSD
tHD
tw
SDI
B15 B14 B13 B12-B2 B1
B0
MSB
LOAD MSB FIRST, LSB LAST
LSB
5
t
FN7393.1
August 1, 2005
5 Page 
EL5525
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN7393.1
August 1, 2005
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet EL5525.PDF ] | |
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