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PDF ISL12020 Data sheet ( Hoja de datos )

Número de pieza ISL12020
Descripción Low Power RTC
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL12020 Hoja de datos, Descripción, Manual

ISL12020
®
Real Time Clock with On Chip Temp Compensation ±5ppm
Data Sheet
March 29, 2007
FN6450.0
Low Power RTC with VDD Battery Backed
SRAM and Embedded Temp
Compensation ±5ppm with Auto Day Light
Saving
The ISL12020 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brown out
indicator, single periodic or polled alarms, intelligent battery
backup switching and 128 bytes of battery-backed user
SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically,
using parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
battery power, and also from battery to VDD power.
Pinoutwww.DataSheet4U.com
ISL12020
(8 LD SOIC)
TOP VIEW
X1
X2
VBAT
GND
1
2
3
4
8 VDD
7 IRQ/FOUT
6 SCL
5 SDA
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating
Temp Range
- ±5ppm over -20°C to +70°C
• Day Light Saving Time
- Customer Programmable
• 15 Selectable Frequency Outputs
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Cap
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor, 2 Levels, Selectable by Customer
to:
- Seven Selectable Voltages for Each Level
• Power Status Brown Out Monitor
• Six Selectable Trip Level, from 4.675V to 2.295V Power
Failure Detection
• Time Stamp during Power to Battery and Battery to Power
Cross Over
- Time Stamp. First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Clock Frequency
• 8 Ld SOIC Package ISL12020
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• POS Equipment
• Medical Application
• Security Related Application
• Vending Machine
• White Goods
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




ISL12020 pdf
ISL12020
I2C Interface Specifications Test Conditions: VDD=+2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 7) MAX UNITS NOTES
tDH Output Data Hold Time
From SCL falling edge
crossing 30% of VDD, until
SDA enters the 30% to 70%
of VDD window.
0
tR SDA and SCL Rise Time
From 30% to 70% of VDD. 20 + 0.1 x Cb
tF SDA and SCL Fall Time
From 70% to 30% of VDD. 20 + 0.1 x Cb
Cb Capacitive loading of SDA or SCL Total on-chip and off-chip
10
ns
300 ns
300 ns
400 pF
RPU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by
tR and tF.
For Cb = 400pF, max is about
2~2.5kΩ.
For Cb = 40pF, max is about
15~20kΩ
1
kΩ
NOTES:
2. Temperature Conversion is inactive below 2.7V VBAT
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), VBAT 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
5 FN6450.0
March 29, 2007

5 Page





ISL12020 arduino
ISL12020
REG
ADDR. SECTION NAME
7
00h SC 0
01h MN 0
02h HR MIL
03h RTC
DT
0
04h MO 0
05h YR YR23
06h DW 0
07h SR BUSY
08h INT ARST
09h PWR_VDD CLRTS
0Ah PWR_VBAT BSW
0Bh CSR
ITRO IDTR01
0Ch
ALPHA
D
0Dh
BETA
TSE
0Eh
FATR
0
0Fh
FDTR
0
10h
SCA0
ESCA0
11h MNA0 EMNA0
12h HRA0
ALARM
13h DTA0
EHRA0
EDTA0
14h MOA0 EMOA00
15h DWA0 EDWA0
16h VSC 0
17h VMN 0
18h TSV2B
VHR
VMIL
19h VDT 0
1Ah VMO 0
1Bh BSC 0
1Ch BMN 0
1Dh TSB2V
BHR
BMIL
1Eh BDT 0
1Fh BMO 0
TABLE 1. REGISTER MEMORY MAP
BIT
6
SC22
5
SC21
4
SC20
3
SC13
2
SC12
MN22
MN21
MN20
MN13
MN12
0
HR21
HR20
HR13
HR12
0
DT21
DT20
DT13
DT12
0
0
MO20
MO13
MO12
YR22
YR21
YR20
YR13
YR12
0 0 0 0 DW2
OSCF DSTADJ
ALM
LVDD
LBAT85
WRTC
IM
FOBATB
FO3
FO2
D D D D VDDTrip2
D VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2
IDTR00 IATR05 IATR04 IATR03 IATR02
ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2
BTSE
BTSR
D
BETA3
BETA2
0
FFATR5 FATR4
FATR3
FATR2
0 0 0 0 FDTR2
SCA022 SCA021 SCA020 SCA013 SCA012
MNA022 MNA021 MNA020 MNA013 MNA012
D HRA021 HRA020 HRA013 HRA012
D DTA021 DTA020 DTA013 DTA012
D D MOA020 MOA013 MOA012
D D D D DWA02
VSC22
VSC21
VSC20
VSC13
VSC12
VMN22 VMN21 VMN20 VMN13 VMN12
0
VHR21
VHR20
VHR13
VHR12
0
VDT21
VDT20
VDT13
VDT12
0 0 VMO20 VMO13 VMO12
BSC22
BSC21
BSC20
BSC13
BSC12
BMN22 BMN21 BMN20 BMN13 BMN12
0
BHR21
BHR20
BHR13
BHR12
0
BDT21
BDT20
BDT13
BDT12
0 0 BMO20 BMO13 BMO12
1
SC11
MN11
HR11
DT11
MO11
YR11
DW1
LBAT75
FO1
VDDTrip1
VB75Tp1
IATR01
ALPHA1
BETA1
FATR1
FDTR1
SCA011
MNA011
HRA011
DTA011
MOA011
DWA01
VSC11
VMN11
VHR11
VDT11
VMO11
BSC11
BMN11
BHR11
BDT11
BMO11
0
SC10
MN10
HR10
DT10
MO10
YR10
DW0
RTCF
FO0
VDDTrip0
VB75Tp0
IATR00
ALPHA0
BETA0
FATR0
FDTR0
SCA010
MNA010
HRA010
DTA010
MOA010
DWA00
VSC10
VMN10
VHR10
VDT10
VMO10
BSC10
BMN10
BHR10
BDT10
BMO10
RANGE DEFAULT
0 to 59
00h
0 to 59
00h
0 to 23
00h
1 to 31
01h
1 to 12
01h
0 to 99
00h
0 to 6
00h
N/A 01h
N/A 00h
N/A 00h
N/A 00h
N/A 08h
N/A 25h
N/A 08h
N/A 00h
N/A 00h
00 to 59
00h
00 to 59
00h
0 to 23
00h
01 to 31
01h
01 to 12
01h
0 to 6
00h
0 to 59
00h
0 to 59
00h
0 to 23
00h
1 to 31
00h
1 to 12
00h
0 to 59
00h
0 to 59
00h
0 to 23
00h
1 to 31
00h
1 to 12
00h
11 FN6450.0
March 29, 2007

11 Page







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