|
|
PDF FAN5069 Data sheet ( Hoja de datos )
| Número de pieza | FAN5069 | |
| Descripción | PWM and LDO Controller Combo | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de FAN5069 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
FAN5069
PWM and LDO Controller Combo
September 2006
www.DataSheet4U.com
Features
■ General Purpose PWM Regulator and LDO Controller
■ Input Voltage Range: 3V to 24V
■ Output Voltage Range: 0.8V to 15V
– VCC
– 5V
■ Shunt Regulator for 12V Operation
■ Support for Ceramic Cap on PWM Output
■ Programmable Current Limit for PWM Output
■ Programmable Switching Frequency (200KHz to
600KHz)
■ RDS(ON) Current Sensing
■ Internal Synchronous Boot Diode
■ Soft-Start for both PWM and LDO
■ Multi-Fault Protection with Optional Auto-restart
■ 16-pin TSSOP Package
Applications
■ PC/Server Motherboard Peripherals
– VCC_MCH (1.5V), VDDQ (1.5V) and
VTT_GTL (1.25V)
■ Power Supply for
– FPGA, DSP, Embedded Controllers, Graphic Card
Processor, and Communication Processors
■ Industrial Power Supplies
■ High-Power DC-to-DC Converters
Description
The FAN5069 combines a high-efficiency Pulse-Width-
Modulated (PWM) controller and an LDO (Low DropOut)
linear regulator controller. Synchronous rectification pro-
vides high efficiency over a wide range of load currents.
Efficiency is further enhanced by using the low-side
MOSFET’s RDS(ON) to sense current.
Both the linear and PWM regulator soft-start are con-
trolled by a single external capacitor, to limit in-rush cur-
rent from the supply when the regulators are first
enabled. Current limit for PWM is also programmable.
The PWM regulator employs a summing-current-mode
control with external compensation to achieve fast load
transient response and provide design optimization.
FAN5069 is offered in both industrial temperature grade
(-40°C to +85°C) as well as commercial temperature
grade (-10°C to +85°C).
Ordering Information
Part Number Operating Temp. Range Pb-Free Package Packing Method
FAN5069MTCX
-10°C to +85°C
Yes 16-Lead TSSOP Tape and Reel
FAN5069EMTCX
-40°C to +85°C
Yes 16-Lead TSSOP Tape and Reel
Qty./Reel
2500
2500
Note: Contact Fairchild sales for availability of other package options.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
1 page  
Electrical Characteristics
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Parameter
Conditions
Min.
Supply Current
IVCC
IVCC(SD)
IVCC(OP)
VCC Current (Quiescent)
VCC Current (Shutdown)
VCC Current (Operating)
VSHUNT VCC Voltage(6)
HDRV, LDRV Open
EN = 0V, VCC = 5.5V
EN = 5V, VCC = 5.0V,
QFET = 20nC, FSW = 200kHz
Sinking 1mA to 100mA at VCC
Pin
•
•
2.6
5.5
Under-Voltage Lockout (UVLO)
UVLO(H)
UVLO(L)
Rising VCC UVLO Threshold
Falling VCC UVLO Threshold
VCC UVLO Threshold
Hysteresis
• 4.00
• 3.60
Soft-Start
ISS Current
VLDOSTART LDO Start Threshold
VSSOK PWM Protection Enable
Threshold
Oscillator
FOSC Frequency
R(T) = 56KΩ ± 1%
R(T) = Open
240
160
Frequency Range
160
ΔVRAMP Ramp Amplitude
(Peak-to-Peak)
R(RAMP) = 330KΩ
Minimum ON Time
F = 200kHz
Reference
VREF
Reference Voltage
(Measured at FB Pin)
Current Amplifier Reference
(at SW node)
TA = 0°C to 70°C
TA = -40°C to 85°C
• 790
• 788
Error Amplifier
DC Gain
GBWP Gain-BW Product
S/R Slew Rate
10pF across COMP to GND
Output Voltage Swing
No Load
• 0.5
IFB FB Pin Source Current
Gate Drive
RHUP
RHDN
RLUP
RLDN
HDRV Pull-up Resistor
HDRV Pull-down Resistor
LDRV Pull-up Resistor
LDRV Pull-down Resistor
Sourcing
Sinking
Sourcing
Sinking
•
•
•
•
Typ.
3.2
200
10
4.25
3.75
0.50
10
2.2
1.2
300
200
0.4
200
800
800
160
80
25
8
1
1.8
1.8
1.8
1.2
Max. Unit
3.8 mA
400 μA
15 mA
5.9 V
4.50 V
4.00 V
V
μA
V
V
360 KHz
240 KHz
600 KHz
V
nS.
810 mV
812 mV
mV
dB
MHz
V/μS.
4.0 V
μA
3.0 Ω
3.0 Ω
3.0 Ω
2.0 Ω
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
5
www.fairchildsemi.com
5 Page 
PWM Operation
Refer to Figure 20 for the PWM control mechanism. The
FAN5069 uses the summing mode method of control to
generate the PWM pulses. The amplified output of the
current-sense amplifier is summed with an internally
generated ramp and the combined signal is amplified
and compared with the output of the error amplifier to get
the pulse width to drive the high-side MOSFET. The
sensed current from the previous cycle is used to modu-
late the output of the summing block. The output of the
summing block is also compared against the voltage
threshold set by the RLIM resistor to limit the inductor cur-
rent on a cycle-by-cycle basis. The controller facilitates
external compensation for enhanced flexibility.
Initialization
When the PWM is disabled, the SW node is connected
to GND through an internal 500Ω MOSFET to slowly dis-
charge the output. As long as the PWM controller is
enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high,
the circuit releases SS and enables the PWM regulator.
The capacitor connected to the SS pin and GND is
charged by a 10µA internal current source, causing the
voltage on the capacitor to rise. When this voltage
exceeds 1.2V, all protection circuits are enabled. When
this voltage exceeds 2.2V, the LDO output is enabled.
The input to the error amplifier at the non-inverting pin is
clamped by the voltage on the SS pin until it crosses the
reference voltage.
The time it takes the PWM output to reach regulation
(TRise) is calculated using the following equation:
TRISE = 8 × 10–2 × CSS (CSS is in μf)
(EQ. 2)
Oscillator Clock Frequency (PWM)
The clock frequency on the oscillator is set using an
external resistor, connected between R(T) pin and
ground. The frequency follows the graph, as shown in
Figure 18. The minimum clock frequency is 200KHz,
which is when R(T) pin is left open. Select the value of
R(T) as shown in the equation below. This equation is
valid for all FOSC > 200kHz.
R(T) = (---F----O----S---C---5--–--×---2--1-0---00---9--×-----1---0----3---)Ω
(EQ. 3)
where FOSC is in Hz.
For example, for FOSC = 300kHz, R(T) = 50KΩ.
RRAMP Selection and Feed-Forward Operation
The FAN5069 provides for input voltage feed-forward
compensation through RRAMP. The value of RRAMP effec-
tively changes the slope of the internal ramp, minimizing
the variation of the PWM modulator gain when input volt-
age varies. The RRAMP also has an effect on the current
limit, as can be seen in the RLIM equation (EQ. 5). The
RRAMP value can be approximated using the following
equation:
RRAMP = 6----.-3-----•--V---1-I--N0----––--8---1-•--.--8F----o----s----c- KΩ
(EQ. 4)
where FOSC is in Hz. For example, for FOSC = 300kHz
and VIN = 12V, RRAMP ≈ 540KΩ.
Gate Drive Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
and provides necessary amplification, level shifting, and
shoot-through protection. It also has functions that help
optimize the IC performance over a wide range of oper-
ating conditions. Since the MOSFET switching time can
vary dramatically from device to device and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than approxi-
mately 1V. Similarly, the upper MOSFET is not turned on
until the gate-to-source voltage of the lower MOSFET
has decreased to less than approximately 1V. This
allows a wide variety of upper and lower MOSFETs to be
used without a concern for simultaneous conduction, or
shoot-through.
A low impedance path between the driver pin and the
MOSFET gate is recommended for the adaptive dead-
time circuit to work properly. Any delay along this path
reduces the delay generated by the adaptive dead-time
circuit, thereby increasing the chances for shoot-through.
Protection
In the FAN5069, the converter is protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions. All of these conditions generate an
internal “fault latch” which shuts down the converter. For
all fault conditions both the high-side and the low-side
drives are off except in the case of OVP where the low-
side MOSFET is turned on until the voltage on the FB pin
goes below 0.4V. The fault latch can be reset either by
toggling the EN pin or recycling VCC to the chip.
Over Current Limit (PWM)
The PWM converter is protected against overloading
through a cycle-by-cycle current limit set by selecting
RILIM resistor. An internal 10µA current source sets the
threshold voltage for the output of the summing amplifier.
When the summing amplifier output exceeds this thresh-
old level, the current limit comparator trips and the PWM
starts skipping pulses. If the current limit tripping occurs
for 16 continuous clock cycles, a fault latch is set and the
controller shuts down the converter. This shutdown fea-
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet FAN5069.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| FAN5063 | ACPI Dual Switch Controller | Fairchild Semiconductor |
| FAN5066 | Ultra Low Voltage Synchronous DC-DC Controller | Fairchild Semiconductor |
| FAN5067 | ACPI Dual Switch Controller | Fairchild Semiconductor |
| FAN5068 | DDR-1/DDR-2 plus ACPI Regulator Combo | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |