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PDF ISL22346 Data sheet ( Hoja de datos )

Número de pieza ISL22346
Descripción Dual Digitally Controlled Potentiometers
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL22346 Hoja de datos, Descripción, Manual

ISL22346
® Quad Digitally Controlled Potentiometers (XDCP™)
Data Sheet
July 28, 2006
FN6177.0
Low Noise, Low Power I2C® Bus, 128 Taps
The ISL22346 integrates four digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as a three-terminal potentiometers
or as a two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Pinout
www.DataSheet4U.com
ISL22346
(20 LD TSSOP)
TOP VIEW
RH3
RL3
RW3
A2
SCL
SDA
GND
RW2
RL2
RH2
1
2
3
4
5
6
7
8
9
10
20 RW0
19 RL0
18 RH0
17 SHDN
16 VCC
15 A1
14 A0
13 RH1
12 RL1
11 RW1
Features
• Four potentiometers in one package
• 128 resistor taps
• I2C serial interface
- Three address pins, up to eight devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10ktotal resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T <55°C
• 20 Ld TSSOP
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(k)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22346UFV20Z
(Notes 1, 2)
22346 UFVZ
50
-40 to +125
20 Ld TSSOP
M20.173
(Pb-Free)
ISL22346WFV20Z
(Notes 1, 2)
22346 WFVZ
10
-40 to +125
20 Ld TSSOP
M20.173
(Pb-Free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




ISL22346 pdf
ISL22346
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5) MAX
tWC Non-volatile Write Cycle Time
(Note 20)
12 20
SERIAL INTERFACE SPECS
VIL A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3 0.3*VCC
VIH A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
VCC+0.3
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*
VCC
0
0.4
Cpin A2, A1, A0, SHDN, SDA, and SCL Pin
(Note 19) Capacitance
10
fSCL
tsp
(Note 19)
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
400
50
tAA
tBUF
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until
Valid
SDA exits the 30% to 70% of VCC window
Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
900
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO
tHD:STO
tDH
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
Output Data Hold Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
600
1300
0
tR SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
tF SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
10 400
Rpu SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF
Off-chip
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
tSU:A A2, A1 and A0 Setup Time
Before START condition
600
UNIT
ms
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
k
ns
5 FN6177.0
July 28, 2006

5 Page





ISL22346 arduino
ISL22346
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 17).
The ISL22346 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22346 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB is the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation (See Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
Logic values at pins A2, A1, and A0 respectively
1 0 1 0 A2 A1 A0 R/W
(MSB)
(LSB)
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
SDA OUTPUT FROM
TRANSMITTER
1
89
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
WRITE
S
T
A IDENTIFICATION
R BYTE
T
ADDRESS
BYTE
1 0 1 0 A2 A1 A0 0 0 0 0 0
A
C
K
A
C
K
FIGURE 18. BYTE WRITE SEQUENCE
DATA
BYTE
S
T
O
P
A
C
K
11 FN6177.0
July 28, 2006

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