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PDF ISL22329 Data sheet ( Hoja de datos )
| Número de pieza | ISL22329 | |
| Descripción | Dual Digitally Controlled Potentiometers | |
| Fabricantes | Intersil Corporation | |
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ISL22329
® Dual Digitally Controlled Potentiometers (XDCP™)
Data Sheet
September 26, 2006
FN6330.1
Low Noise, Low Power, I2C® Bus, 128 Taps,
Wiper Only
The ISL22329 integrates two digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
Pinout
ISL22329
(10 LD MSOP)
TOP VIEW
www.DataSheet4U.com
A2
SCL
SDA
GND
RW1
1
2
3
4
5
10 RW0
9 SHDN
8 VCC
7 A1
6 A0
Features
• Two potentiometers in one package
• 128 resistor taps
• I2C serial interface
- Three address pins, up to eight devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T < +55°C
• 10 Ld MSOP
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(kΩ)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22329UFU10Z
(Notes 1, 2)
329UZ
50
-40 to +125
10 Ld MSOP
M10.118
(Pb-free)
ISL22329WFU10Z
(Notes 1, 2)
329WZ
10
-40 to +125
10 Ld MSOP
M10.118
(Pb-free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22329
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5) MAX
SERIAL INTERFACE SPECS
VIL A2, A1, A0, SDA, and SCL Input
Buffer Low Voltage
-0.3 0.3*VCC
VIH A2, A1, A0, SDA, and SCL Input
Buffer High Voltage
0.7*VCC
VCC+0.3
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*
VCC
0
0.4
Cpin A2, A1, A0, SDA, and SCL Pin
(Note 12) Capacitance
10
fSCL
tsp
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
400
50
tAA
tBUF
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until
Valid
SDA exits the 30% to 70% of VCC window
Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
900
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO
tHD:STO
tDH
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
or Volatile Only Write
both crossing 70% of VCC
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
600
1300
0
tR SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
tF SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
10 400
Rpu SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF
Off-chip
For Cb = 400pF, max is about 2~2.5kΩ
For Cb = 40pF, max is about 15~20kΩ
1
UNIT
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
5 FN6330.1
September 26, 2006
5 Page 
ISL22329
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
WRITE
S
T
A IDENTIFICATION
R BYTE
T
ADDRESS
BYTE
1 0 1 0 A2 A1 A0 0 0 0 0 0
A
C
K
A
C
K
FIGURE 14. BYTE WRITE SEQUENCE
DATA
BYTE
S
T
O
P
A
C
K
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R BYTE WITH
T R/W=0
ADDRESS
BYTE
S
T
A IDENTIFICATION
R BYTE WITH
T R/W = 1
A
C
K
SIGNAL AT SDA 1 0 1 0 A2 A1 A0 0
0000
SIGNALS FROM
THE SLAVE
A
C
K
1 0 1 0 A2 A1 A0 1
AA
C C FIRST READ
K K DATA BYTE
FIGURE 15. READ SEQUENCE
A
C
K
S
AT
CO
KP
LAST READ
DATA BYTE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22329 responds with an ACK. At this time, the device
enters its standby state (See Figure 14). Device can receive
more than one byte of data by auto incrementing the
address after each received byte. Note after reaching the
address 08h, the internal pointer “rolls over” to address 00h.
Non-volatile write cycle starts after STOP condition is
determined and it requires up to 20 ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 15). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22329 responds with an ACK. Then the ISL22329
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 08h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.The master terminates the read
operation (issuing a ACK and STOP condition) following the
last bit of the last Data Byte (See Figure 15).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 08h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
11 FN6330.1
September 26, 2006
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL22329.PDF ] | |
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