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PDF ISL22326 Data sheet ( Hoja de datos )
| Número de pieza | ISL22326 | |
| Descripción | Dual Digitally Controlled Potentiometers | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL22326
Dual Digitally Controlled Potentiometers (XDCP™)
September 9, 2015
FN6176.3
Low Noise, Low Power, I2C™ Bus, 128 Taps
The ISL22326 integrates two digitally controlled potentiometers
(XDCP) and non-volatile memory on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Pinouts
VCC
SHDN
RH0
RL0
RW0
A2
SCL
ISL22326
(14 LD TSSOP)
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
A1
A0
RH1
RL1
RW1
GND
SDA
Features
• Two potentiometers in one package
• 128 resistor taps
• I2C serial interface
- Three address pins, up to eight devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70 typical @ VCC = 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10k total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T < +55°C
• 14 Ld TSSOP or 16 Ld QFN package
• Pb-free (RoHS compliant)
ISL22326
(16 LD QFN)
TOP VIEW
16 15 14 13
RH0 1
12 RH1
RL0 2
RW0 3
11 RL1
10 RW1
NC 4
9 NC
5678
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2006, 2008, 2009, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22326
Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX
(Note 20) (Note 4) (Note 20) UNIT
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0 or 1)
RINL Integral Non-linearity
(Note 15)
DCP register set between 10h and 7Fh;
monotonic over all tap positions
-1
1 MI
(Note 12)
RDNL Differential Non-linearity
(Note 14)
DCP register set between 10h and 7Fh;
monotonic over all tap positions, W option
-1
1 MI
(Note 12)
DCP register set between 10h and 7Fh;
monotonic over all tap positions, U option
-0.5
0.5 MI
(Note 12)
Roffset Offset
(Note 13)
W option
0 1 5 MI
(Note 12)
U option
0 0.5 2 MI
(Note 12)
RMATCH DCP to DCP Matching
(Note 16)
Any two DCPs at the same tap position with
the same terminal voltages
-2
2 MI
(Note 12)
Operating Specifications Over the recommended operating conditions, unless otherwise specified.
SYMBOL
ICC1
ICC2
ISB
PARAMETER
VCC Supply Current (Volatile
Write/Read)
VCC Supply Current (Non-volatile
Write/Read)
VCC Current (Standby)
ISD VCC Current (Shutdown)
TEST CONDITIONS
fSCL = 400kHz; SDA = Open; (for I2C, active,
read and write states)
fSCL = 400kHz; SDA = Open; (for I2C, active,
read and write states)
VCC = +5.5V @ +85°C, I2C interface in
standby state
VCC = +5.5V @ +125°C, I2C interface in
standby state
VCC = +3.6V @ +85°C, I2C interface in
standby state
VCC = +3.6V @ +125°C, I2C interface in
standby state
VCC = +5.5V @ +85°C, I2C interface in
standby state
VCC = +5.5V @ +125°C, I2C interface in
standby state
VCC = +3.6V @ +85°C, I2C interface in
standby state
VCC = +3.6V @ +125°C, I2C interface in
standby state
MIN
(Note 20)
TYP
(Note 4)
MAX
(Note 20)
0.5
3
5
7
3
5
3
5
2
4
ILkgDig
Leakage Current, at Pins A0, A1, A2, Voltage at pin from GND to VCC
SHDN, SDA and SCL
-1
1
tWRT
DCP Wiper Response Time
(Note 19)
SCL falling edge of last bit of DCP data byte
to wiper new position
1.5
tShdnRec DCP Recall Time from Shutdown
(Note 19) Mode
From rising edge of SHDN signal to wiper
stored position and RH connection
1.5
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
1.5
Vpor Power-on Recall Voltage
Minimum VCC at which memory recall
occurs
2.0
2.6
VccRamp VCC Ramp Rate
0.2
UNIT
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
µs
µs
V
V/ms
5 FN6176.3
September 9, 2015
5 Page 
ISL22326
Pin Descriptions
Potentiometers Pins
RHI AND RLI (i = 0, 1)
The high (RHi) and low (RLi) terminals of the ISL22326 are
equivalent to the fixed terminals of a mechanical potentiometer.
RHi and RLi are referenced to the relative position of the wiper
and not the voltage potential on the terminals. With WRi set to
127 decimal, the wiper will be closest to RHi, and with the WRi
set to 0, the wiper is closest to RLi.
RWI (i = 0,1)
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition on RHi and shorts RWi to RLi. When SHDN is
returned to logic high, the previous latch settings put RWi at
the same resistance setting prior to shutdown. This pin is
logically ANDed with SHDN bit in ACR register. I2C interface
is still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.
RH
RW
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, operation code, wiper
address and data from an I2C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
SERIAL CLOCK (SCL)
This is the serial clock input of the I2C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
DEVICE ADDRESS (A2 - A0)
The address inputs are used to set the least significant 3 bits
of the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22326. A maximum of 8 ISL22326 devices may occupy
the I2C serial bus.
Principles of Operation
The ISL22326 is an integrated circuit incorporating two
DCPs with their associated registers, non-volatile memory
and an I2C serial interface providing direct communication
between a host and the potentiometers and memory. The
resistor arrays are comprised of individual resistors
connected in series. At either end of the array and between
each resistor is an electronic switch that transfers the
potential at that point to the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and
loaded into the corresponding WRi to set the wipers to the
initial value.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper
terminal (RW) is closest to its “Low” terminal (RL). When the
WR register of a DCP contains all ones (WR[6:0] = 7Fh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL22326 is being powered up, all WRs are reset
to 40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, all WRs will be reload with the value stored in
corresponding non-volatile Initial Value Registers (IVRs).
The WRs can be read or written to directly using the I2C
serial interface as described in the following sections. The
I2C interface Address Byte has to be set to 00h or 01h to
access the WR of DCP0 or DCP1 respectively.
Memory Description
The ISL22326 contains seven non-volatile and three volatile
8-bit registers. Memory map of ISL22326 is on Table 1. The
two non-volatile registers (IVRi) at address 0 and 1, contain
initial wiper value and volatile registers (WRi) contain current
wiper position. In addition, five non-volatile General Purpose
registers from address 2 to address 6 are available.
11 FN6176.3
September 9, 2015
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL22326.PDF ] | |
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