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PDF USB3250 Data sheet ( Hoja de datos )
| Número de pieza | USB3250 | |
| Descripción | USB2.0 PHY IC | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de USB3250 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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GT3200
(64-PIN TQFP PACKAGES)
USB3250
(56-PIN QFN PACKAGE)
USB2.0 PHY IC
PRODUCT FEATURES
USB-IF "Hi-Speed" certified to USB2.0 electrical
specification
Interface compliant with the UTMI specification
(60MHz 8-bit unidirectional interface or 30MHz 16-bit
bidirectional interface)
Supports 480Mbps High Speed (HS) and 12Mbps
Full Speed (FS) serial data transmission rates
Integrated 45Ω and 1.5kΩ termination resistors
reduce external component count
Internal short circuit protection of DP and DM lines
On-chip oscillator operates with low cost 12MHz
crystal
Robust and low power digital clock and data recovery
circuit
SYNC and EOP generation on transmit packets and
detection on receive packets
Datasheet
NRZI encoding and decoding
Bit stuffing and unstuffing with error detection
Supports the USB suspend state, HS detection, HS
Chirp, Reset and Resume
Support for all test modes defined in the USB2.0
specification
Draws 72mA (185mW) maximum current
consumption in HS mode - ideal for bus powered
functions
On-die decoupling capacitance and isolation for
immunity to digital switching noise
Available in three 64-pin TQFP packages (GT3200)
or a 56-pin QFN package (USB3250)
Full industrial operating temperature range from
-40oC to +85oC (ambient)
SMSC GT3200, SMSC USB3250
DATASHEET
Revision 1.5 (03-24-06)
1 page  
USB2.0 PHY IC
Datasheet
List of Tables
Table 4.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4.4 Biasing and Clock Oscillator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4.5 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6.1 Electrical Characteristics: Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6.2 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6.5 Dynamic Characteristics: Digital UTMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6.6 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6.7 Eye Pattern for Receive Waveform and Eye Pattern Definition. . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8.1 Linestate States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8.3 USB2.0 Test Mode to Macrocell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SMSC GT3200, SMSC USB3250
5
DATASHEET
Revision 1.5 (03-24-06)
5 Page 
USB2.0 PHY IC
Datasheet
NAME
DATA[15:0]
DIRECTION
Bidir
TXVALID
Input
TXREADY
Output
VALIDH
Bidir
RXVALID
Output
RXACTIVE
RXERROR
Output
Output
SMSC GT3200, SMSC USB3250
Table 4.2 Data Interface Signals
ACTIVE
LEVEL
N/A
High
High
N/A
High
High
High
DESCRIPTION
DATA BUS. 16-BIT BIDIRECTIONAL MODE.
TXVALID
0
0
RXVALID
0
1
01
1X
1X
VALIDH
X
0
1
0
1
DATA[15:0]
Not used
DATA[7:0] output is valid
for receive
VALIDH is an output
DATA[15:0] output is
valid for receive
VALIDH is an output
DATA[7:0] input is valid
for transmit
VALIDH is an input
DATA[15:0] input is valid
for transmit
VALIDH is an input
DATA BUS. 8-BIT UNIDIRECTIONAL MODE.
TXVALID RXVALID DATA[15:0]
0 0 Not used
0 1 DATA[15:8] output is valid for receive
1 X DATA[7:0] input is valid for transmit
Transmit Valid. Indicates that the TXDATA bus is valid for
transmit. The assertion of TXVALID initiates the transmission of
SYNC on the USB bus. The negation of TXVALID initiates EOP
on the USB.
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT)
must not be changed on the de-assertion or assertion of TXVALID.
The PHY must be in a quiescent state when these inputs are
changed.
Transmit Data Ready. If TXVALID is asserted, the SIE must
always have data available for clocking into the TX Holding
Register on the rising edge of CLKOUT. TXREADY is an
acknowledgement to the SIE that the transceiver has clocked the
data from the bus and is ready for the next transfer on the bus. If
TXVALID is negated, TXREADY can be ignored by the SIE.
Transmit/Receive High Data Bit Valid (used in 16-bit mode
only). When TXVALID = 1, the 16-bit data bus direction is
changed to inputs, and VALIDH is an input. If VALIDH is asserted,
DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0]
is valid for transmission. The DATA bus is driven by the SIE.
When TXVALID = 0 and RXVALID = 1, the 16-bit data bus
direction is changed to outputs, and VALIDH is an output. If
VALIDH is asserted, the DATA[15:0] outputs are valid for receive.
If deasseted, only DATA[7:0] is valid for receive. The DATA bus
is read by the SIE.
Receive Data Valid. Indicates that the RXDATA bus has received
valid data. The Receive Data Holding Register is full and ready to
be unloaded. The SIE is expected to latch the RXDATA bus on the
rising edge of CLKOUT.
Receive Active. Indicates that the receive state machine has
detected Start of Packet and is active.
Receive Error. 0: Indicates no error. 1: Indicates a receive error
has been detected. This output is clocked with the same timing as
the RXDATA lines and can occur at anytime during a transfer.
11
DATASHEET
Revision 1.5 (03-24-06)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet USB3250.PDF ] | |
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