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PDF WF2M16-XXX5 Data sheet ( Hoja de datos )

Número de pieza WF2M16-XXX5
Descripción 2Mx16 Flash MODULE
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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No Preview Available ! WF2M16-XXX5 Hoja de datos, Descripción, Manual

White Electronic Designs
WF2M16-XXX5
PRELIMINARY*
2Mx16 Flash MODULE, SMD 5962-97610
FEATURES
Access Times of 90, 120, 150ns
Packaging:
• 56 lead, Hermetic Ceramic, 0.520" CSOP
(Package 207).
Fits standard 56 SSOP footprint.
• 44 pin Ceramic SOJ (Package 102)**
• 44 lead Ceramic Flatpack (Package 208)**
Sector Architecture
• 32 equal size sectors of 64KBytes each
• Any combination of sectors can be erased.
Also supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx16; User Configurable as 2 x 2Mx8
Commercial, Industrial, and Military Temperature
Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation.
RESET# pin resets internal state machine to the
read mode.
Ready/Busy (RY#/BY#) output for detection of
program or erase cycle completion.
Multiple Ground Pins for Low Noise Operation
* This product is under development, is not qualified or characterized and is subject to
change without notice.
** Package to be developed.
Note: For programming information refer to Flash Programming 16M5 Application Notes.
www.DataSheet4U.com
WF2M16-XDAX5
56 CSOP
TOP VIEW
CS1#
A12
A13
A14
A15
NC
CS2#
NC
A20
A19
A18
A17
A16
VCC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY#
OE#
WE#
NC
I/O13
I/O5
I/O12
I/O4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 NC
55 #RESET
54 A11
53 A10
52 A9
51 A1
50 A2
49 A3
48 A4
47 A5
46 A6
45 A7
44 GND
43 A8
42 VCC
41 I/O9
40 I/O1
39 I/O8
38 I/O0
37 A0
36 NC
35 NC
34 NC
33 I/O2
32 I/O10
31 I/O3
30 I/O11
29 GND
April 2004
Rev. 5
FIGURE 1 – PIN CONFIGURATIONS
WF2M16-XXX5
44 CSOJ (DL)**
44 FLATPACK (FL)**
TOP VIEW
PIN DESCRIPTION
I/O0-15
A0-20
WE#
Data Inputs/Outputs
Address Inputs
Write Enable
CS1#
A12
A13
A14
A15
NC
CS2#
NC
A20
A19
A18
A17
A16
VCC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY#
OE#
WE#
NC
I/O13
I/O5
I/O12
I/O4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 NC
55 #RESET
54 A11
53 A10
52 A9
51 A1
50 A2
49 A3
48 A4
47 A5
46 A6
45 A7
44 GND
43 A8
42 VCC
41 I/O9
40 I/O1
39 I/O8
38 I/O0
37 A0
36 NC
35 NC
34 NC
33 I/O2
32 I/O10
31 I/O3
30 I/O11
29 GND
** Package to be developed.
CS1-2#
OE#
VCC
VSS
RY/BY#
RESET#
Chip Select
Output Enable
Power Supply
Ground
Ready/Busy
Reset
BLOCK DIAGRAM
I/O0-7
I/O8-1
RESET#
WE#
OE#
A0-20
RY/BY#
2M x 8
2M x 8
CS1#
CS2#
NOTE:
1. RY/BY# is an open drain output and should be pulled up to Vcc with an external resistor.
2. Address compatible with Intel 2M8 56 SSOP.
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




WF2M16-XXX5 pdf
White Electronic Designs
WF2M16-XXX5
PRELIMINARY
FIGURE 3 – AC WAVEFORMS FOR READ OPERATIONS
April 2004
Rev. 5
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





WF2M16-XXX5 arduino
White Electronic Designs
PACKAGE 207: 56 LEAD, CERAMIC SOP*
WF2M16-XXX5
PRELIMINARY
23.63 (0.930) ± 0.25 (0.010)
21.59 (0.850) TYP
16.13 (0.635)
± 0.13 (0.005)
12.96 (0.510)
± 0.15 (0.006)
0.18 (0.007)
± 0.03 (0.001)
0.51 (0.020)
± 0.13 (0.005)
a
3.43 (0.120)
± 0.38 (0.015)
0.51 (0.020)
± 0.13 (0.005)
+
PIN 1
IDENTIFIER
0.80 (0.031) TYP
* Package Dimensions subject to change
1.60 (0.063) TYP
0.25 (0.010)
± 0.05 (0.002)SEE DETAIL "A"
3.57 (0.140)
± 0.51 (0.020)
0 / -4
DETAIL "A"
0.51
(0.020)
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
FIGURE 8 – ALTERNATE PIN CONFIGURATION FOR WF2M16W-XDAX5
56 CSOP
TOP VIEW
CS1#
A12
A13
A14
A15
NC
CS2#
A21
A20
A19
A18
A17
A16
VCC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY#
OE#
WE#
NC
I/O13
I/O5
I/O12
I/O4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 NC
55 RESET#
54 A11
53 A10
52 A9
51 A1
50 A2
49 A3
48 A4
47 A5
46 A6
45 A7
44 GND
43 A8
42 VCC
41 I/O9
40 I/O1
39 I/O8
38 I/O0
37 NC
36 NC
35 NC
34 NC
33 I/O2
32 I/O10
31 I/O3
30 I/O11
29 GND
BLOCK DIAGRAM
I/O0-7
I/O8-15
RESET#
WE#
OE#
A1-21
RY/BY#
2M x 8
2M x 8
CS1#
CS2#
PIN DESCRIPTION
I/O0-15
A0-21
WE#
CS1-2#
OE#
VCC
VSS
RY/BY#
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Ready/Busy
Reset
NOTE:
1. RY/BY# is an open drain output and should be pulled
up toVcc with an external resistor.
2. Address compatible with Intel 1M16 56 SSOP.
April 2004
Rev. 5
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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