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PDF EM638325 Data sheet ( Hoja de datos )
| Número de pieza | EM638325 | |
| Descripción | 2M x 32 Synchronous DRAM | |
| Fabricantes | Etron Technology | |
| Logotipo |  |
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EtronTech
EM638325
2M x 32 Synchronous DRAM (SDRAM)
Preliminary (Rev 1.4 October/2005)
Features
• Clock rate: 200/183/166/143/125/100 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Four internal banks (512K x 32bit x 4bank)
• Programmable Mode
- CAS# Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
• Burst stop function
• Individual byte controlled by DQM0-3
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• Package: 400 x 875 mil, 86 Pin TSOP II, 0.50mm
pin pitch
• Lead Free Package available
Ordering Information
Part Number
Leaded / Lead Free Package
EM638325TS-5/-5G
EM638325TS-5.5/-5.5G
EM638325TS-6/-6G
EM638325TS-7/-7G
EM638325TS-8/-8G
EM638325TS-10/-10G
Frequency
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
Package
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86 VSS
8 5 DQ15
84 VSSQ
8 3 DQ14
8 2 DQ13
8 1 VDDQ
8 0 DQ12
7 9 DQ11
78 VSSQ
7 7 DQ10
7 6 DQ9
7 5 VDDQ
7 4 DQ8
7 3 NC
72 VSS
71 DQM1
7 0 NC
6 9 NC
6 8 CLK
6 7 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
5 7 NC
5 6 DQ31
5 5 VDDQ
5 4 DQ30
5 3 DQ29
52 VSSQ
5 1 DQ28
5 0 DQ27
4 9 VDDQ
4 8 DQ26
4 7 DQ25
46 VSSQ
4 5 DQ24
44 VSS
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
1 page  
EtronTech
2Mega x 32 SDRAM EM638325
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DQM(6) BS0,1 A10 A9-0 CS# RAS# CAS# WE#
BankActivate
Idle(3)
HXX
V Row address L L H H
BankPrecharge
Any H X X V L X L L H L
PrechargeAll
Any H X X X H X L L H L
W rite
Active(3)
H
X
X
Write and AutoPrecharge
Active(3)
H
X
X
V L Column L H L L
address
V H (A0 ~ A7) L H L L
Read
Active(3)
H
X
X
Read and Autoprecharge
Active(3)
H
X
X
V L Column L H L H
address
V H (A0 ~ A7) L H L H
Mode Register Set
Idle H X X
OP code
LL L L
No-Operation
Any H X X X X X L H H H
Burst Stop
Active(4)
H
X
X
XX
X
LH H L
Device Deselect
Any H X X X X X H X X X
AutoRefresh
Idle H H X X X X L L L H
SelfRefresh Entry
Idle H L X X X X L L L H
SelfRefresh Exit
Idle L H X X X X H X X X
(SelfRefresh)
LH H H
Clock Suspend Mode Entry
Active
H
L
X
XX
X
XX X X
Power Down Mode Entry
Any(5)
HL
X
XX
X HX X X
LH H H
Clock Suspend Mode Exit
Active
LHX
XX
X
XX X X
Power Down Mode Exit
Any L H X X X X H X X X
(PowerDown)
LH H H
Data Write/Output Enable Active H X L X X X X X X X
Data Mask/Output Disable
Active
H
X
H
XX
X
XX X
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
X
Preliminary
5
Rev 1.4
Oct. 2005
5 Page 
EtronTech
2Mega x 32 SDRAM EM638325
7 Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0 T 1
T2 T3
T4 T5
T6 T7
T8
CLK
COMMAND
Bank A
Activate
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
NOP
NOP
Write A
AutoPrecharge
NOP
DIN A0
DIN A1
DIN A0
DIN A1
NOP
tDAL
*
*
NOP
tDAL
NOP
NOP
tDAL= tWR + tRP
* Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)
8 Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A10-A0 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins BS0,1 and A10~A0 in the same cycle is the data written
to the mode register. One clock cycle is required to complete the write in the mode register (refer to
the following figure). The contents of the mode register can be changed using the same command
and the clock cycle requirements during operation as long as all banks are in the idle state.
Preliminary
11
Rev 1.4
Oct. 2005
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet EM638325.PDF ] | |
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