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PDF ICM7231 Data sheet ( Hoja de datos )
| Número de pieza | ICM7231 | |
| Descripción | (ICM7231 / ICM7232) Numeric/Alphanumeric Triplexed LCD Display Drivers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM ICM7231, ICM7232
August 1997
Numeric/Alphanumeric Triplexed
LCD Display Drivers
Features
• ICM7231 Drives 8 Digits of 7 Segments with Two
Independent Annunciators Per Digit Address and Data
Input in Parallel Format
• ICM7232 Drives 10 Digits of 7 Segments with Two
Independent Annunciators Per Digit Address and Data
Input in Serial Format
• All Signals Required to Drive Rows and Columns of
Triplexed LCD Display are Provided
• Display Voltage Independent of Power Supply
• On-Chip Oscillator Provides All Display Timing
• Total Power Consumption Typically 200µW, Maximum
500µW at 5V
• Low-Power Shutdown Mode Retains Data With 5µW
Typical Power Consumption at 5V, 1µW at 2V
• Direct Interface to High-Speed Microprocessors
Description
The ICM7231 and ICM7232 family of integrated circuits are
designed to generate the voltage levels and switching wave-
forms required to drive triplexed liquid-crystal displays.
These chips also include input buffer and digit address
decoding circuitry allowing six bits of input data to be
decoded into 64 independent combinations of the output
segments of the selected digit.
The family is designed to interface to modern high-
performance microprocessors and microcomputers and
ease system requirements for ROM space and CPU time
needed to service a display.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
ICM7231BFIJL
-25 to 85
40 Ld CERDIP
ICM7231BFIPL
-25 to 85
40 Ld PDIP
ICM7232BFIPL
-25 to 85
40 Ld PDIP
ICM7232CRIPL
-25 to 85
40 Ld PDIP
NOTE:
All versions intended for triplexed LCD displays.
NUMBER OF DIGITS
8 Digit
8 Digit
10 Digit
10 Digit
INPUT FORMAT
Parallel
Parallel
Serial
Serial
PKG. NO.
F40.6
E40.6
E40.6
E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
19
FN3161.1
1 page  
ICM7231, ICM7232
Absolute Maximum Ratings
Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . VSS - 0.3 ≤ VIN ≤ 6.5
Display Voltage (Note 1). . . . . . . . . . . . . . . . . . . .0.3 ≤ VDISP ≤ +0.3
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
60
N/A
CERDIP Package . . . . . . . . . . . . . . . .
50
12
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside
the power supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than
-0.3V below ground, but maybe connected to voltages above VDD but not more than 6.5V above VSS.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications V+ = 5V +10%, VSS = 0V, TA = -25oC to 85oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP
Power Supply Voltage, VDD
Data Retention Supply Voltage, VDD
Logic Supply Current, IDD
Shutdown Total Current, IS
Display Voltage Range, VDISP
Display Voltage Setup Current, IDISP
Guaranteed Retention at 2V
Current from VDD to Ground Excluding Display.
VDISP = 2V
VDISP Pin 2 Open
VSS ≤ VDISP ≤ VDD
VDISP = 2V, Current from VDD to VDISP On-
Chip
4.5
2
-
-
0
-
>4
1.6
30
1
-
15
Display Voltage Setup Resistor Value, RD-
ISP
DC Component of Display Signals
One of Three Identical Resistors in String
(Sample Test Only)
40 75
- 1/4
MAX
5.5
-
100
10
VDD
30
-
1
Display Frame Rate, fDISP
Input Low Level, VIL
Input High Level, VIH
Input Leakage, IILK
Input Capacitance, CIN
Output Low Level, VOL
Output High Level, VOH
Operating Temperature Range, TOP
See Figure 5
ICM7231, Pins 30 - 35, 37 - 39, 1
ICM7232, Pins 1, 38, 39 (Note 2)
Pin 37, ICM7232, IOL = 1mA
VDD = 4.5V, IOH = -500µA
Industrial Range
60 90 120
- - 0.8
2.0 -
-
- 0.1 1
-5-
- - 0.4
4.1 -
-
-25 - +85
UNITS
V
V
µA
µA
V
µA
kΩ
% (VDD -
VDISP)
Hz
V
V
µA
pF
V
V
oC
AC Specifications VDD = 5V +10% VSS = 0V, -25oC to 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNITS
PARALLEL INPUT (ICM7231) See Figure 1
Chip Select Pulse Width, tCS
Address/Data Setup Time, tDS
Address/Data Hold Time, tDH
Inter-Chip Select Time, tICS
SERIAL INPUT (ICM7232) See Figures 2, 3
(Note 1)
(Note 1)
(Note 1)
(Note 1)
500 350
200 -
0 -20
3-
-
-
-
-
ns
ns
ns
µs
Data Clock Low Time, tCL
Data Clock High Time, tCL
Data Setup Time, tDS
Data Hold Time, tDH
Write Pulse Width, tWP
Write Pulse to Clock at Initialization, tWLL
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
350 -
350 -
200 -
0 -20
500 350
1.5 -
-
-
-
-
-
-
ns
ns
ns
ns
ns
µs
23
5 Page 
ICM7231, ICM7232
Figure 8 shows the curve of contrast versus applied RMS volt-
age for a liquid
typical value for
crystal material
1/3 multiplexed
tailored for
displays in
VPEAK = 3.1V, a
calculators. Note
that the RMS OFF voltage VPEAK/3 ≈ 1V is just below the
“threshold” voltage where contrast begins to increase. This
places the RMS ON voltage at 2.1V, which provides about
85% contrast when viewed straight on.
0+
specifying displays the following must be kept in mind: liquid
crystal material, polarizer, and seal materials.
A more important effect of temperature is the variation of
threshold voltage. For typical liquid crystal materials suitable for
multiplexing, the peak voltage has a temperature coefficient of -7
to -14mV/oC. This means that as temperature rises, the thresh-
old voltage goes down. Assuming a fixed value for VP, when the
threshold voltage drops below VPEAK/3 OFF segments begin to
be visible. Figure 9 shows the temperature dependence of peak
voltage for the same liquid crystal material of Figure 8.
0-
6
100
TA = 25oC
90
θ = -10o
θ=0
80
70 θ = -30o
60
50 VOFF =
40 1.1VRMS
θ = +10o
30
20 VON = 2.1V
10
0
01234
APPLIED VOLTAGE (VRMS)
FIGURE 8. CONTRAST vs APPLIED RMS VOLTAGE
All members of the ICM7231 and ICM7232 family use an internal
resistor string of three equal value resistors to generate the volt-
ages used to drive the display. One end of the string is con-
nected on the chip to VDD and the other end (user input) is
available at pin 2 (VDISP) on each chip. This allows the display
voltage input (VDISP) to be optimized for the particular liquid crys-
tal material used. Remember that VPEAK = VDD - VDISP and
should be three times the threshold voltage of the liquid crystal
material used. Also it is very important that pin 2 never be driven
below VSS . This can cause device latchup and destruction of the
chip.
Temperature Effects and Temperature Compensation
The performance of the LCD material is affected by tempera-
ture in two ways. The response time of the display to changes
of applied RMS voltage gets longer as the display tempera-
ture drops. At very low temperatures (-20oC) some displays
may take several seconds to change a new character after the
new information appears at the outputs. However, for most
applications above 0oC this will not be a problem with avail-
able multiplexed LCD materials, and for low-temperature
applications, high-speed liquid crystal materials are available.
At high temperature, the effect to consider deals with plastic
materials used to make the polarizer.
Some polarizers become soft at high temperatures and per-
manently lose their polarizing ability, thereby seriously
degrading display contrast. Some displays also use sealing
materials unsuitable for high temperature use. Thus, when
5 PEAK VOLTAGE FOR
90% CONTRAST (ON)
4
3
2
1
PEAK VOLTAGE FOR
10% CONTRAST (OFF)
0
-10 0 10 20 30 40 50
AMBIENT TEMPERATURE (oC)
FIGURE 9. TEMPERATURE DEPENDENCE OF LC THRESHOLD
For applications where the display temperature does not
vary widely, VPEAK may be set at a fixed voltage chosen to
make the RMS OFF voltage, VPEAK/3, just below the
threshold voltage at the highest temperature expected. This
will prevent OFF segments turning ON at high temperature
(this at the cost of reduced contrast for ON segments at low
temperatures).
For applications where the display temperature may vary to
wider extremes, the display voltage VDISP (and thus VPEAK)
may require temperature compensation to maintain sufficient
contrast without OFF segments becoming visible.
Display Voltage and Temperature Compensation
These circuits allow control of the display peak voltage by
bringing the bottom of the voltage divider resistor string out at
pin 2. The simplest means for generating a display voltage
suitable to a particular display is to connect a potentiometer
from pin 2 to VSS as shown in Figure 10. A potentiometer with
a maximum value of 200kΩ should give sufficient range of
adjustment to suit most displays. This method for generating
display voltage should be used only in applications where the
temperature of the chip and display won’t vary more than
±5oC (±9oF), as the resistors on the chip have a positive tem-
perature coefficient, which will tend to increase the display
peak voltage with an increase in temperature. The display
voltage also depends on the power supply voltage, leading to
tighter tolerances for wider temperature ranges.
29
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICM7231.PDF ] | |
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