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PDF LAN91C95 Data sheet ( Hoja de datos )
| Número de pieza | LAN91C95 | |
| Descripción | ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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LAN91C95
ISA/PCMCIA Full Duplex Single-Chip
Ethernet and Modem Controller with RAM
FEATURES
• ISA/PCMCIA Single Chip Ethernet Controller
With Modem Support
• 6 Kbytes Built-In RAM
• Supports IEEE 802.3 (ANSI 8802-3) Ethernet
Standards
• Full Duplex Support
• Hardware Memory Management Unit
• Built-In AUI and 10BASE-T Network Interfaces
• SimultaskingJ - Early Transmit and Early
Receive Functions
• Advanced Power Management
Features/Including Magic Packet Frame
Control
• Software Compatible with LAN91C92/
LAN91C94 (in ISA Mode)
• Configuration Registers Implement Cardbus
Multi-Function Specification V3.0 with
Backward Compatibility to V2.1
• Interfaces Directly to Lucent Technologies and
Conexant (formerly Rockwell) Modem
Chipsets
• On-Chip Attribute Memory (CIS) of up to 512
Bytes (On Even Addresses) For Card
Configuration Information; Expandable
Externally
• Option for Serial or Parallel EEPROM for CIS
• Optional External Flash Capability for XIP
(Execute in Place)
• Automatic Technology to Detect 10 BASE-T
TX/RX Polarity Reversal
• Low Power CMOS Design
• Supports Magic Packet Wakeup
• 128 Pin TQFP Package
Bus Interface
• Direct Interface to ISA and PCMCIA with No
Wait States
• High Impedance Speaker Interface
• Flexible Bus Interface
• 16-Bit Data and Control Paths
• Fast Access Time (40 ns)
• Pipelined Data Path
• Handles Block Word Transfers for Any
Alignment
• High Performance Chained ("Back-to-
Back") Transmit and Receive
• Flat Memory Structure for Low CPU
Overhead
• Dynamic Memory Allocation Between
Transmit and Receive
• Buffered Architecture, Insensitive to Bus
Latencies (No Overruns/Underruns)
• Supports Boot PROM for Diskless ISA
Applications
Simultasking is a trademark and SMSC is a registered trademark of Standard Microsystems Corporation
1 page  
receive are fully independent. It has 6 kbytes of
internal memory and the MMU manages
memory in 256 byte pages. The memory size
accommodates the increase in interrupt latency
resulting from simultaneous LAN and modem
operation as well as the potential for
simultaneous transmit and receive traffice in
some full duplex applications.
The LAN91C95 integrates most of the 802.3
functionality, incorporating the MAC layer
protocol, the physical layer encoding and
decoding functions with the ability to handle the
AUI interface. For twisted pair networks, the
LAN91C95 integrates the twisted pair
transceiver as well as the link integrity test
functions.
Packet reception and transmission are
determined by memory availability. All other
resources are always available if memory is
available. To complement this flexible
architecture, all ISA bus interface functions are
incorporated in the LAN91C95, as well as a 6K
byte packet RAM and serial EEPROM-based
setup. The user can select or modify
configuration choices.
The LAN91C95 is a true 10BASE-T single chip
able to interface a system or a local bus.
Directly-driven LEDs for installation and run-
time diagnostics are provided, as well as 802.3
statistics gathering to facilitate network
management.
The LAN91C95 offers:
The LAN91C95 stores the Configuration High integration:
Information Structure (CIS) on reset or power-up
Single chip adapter including:
from the serial EEPROM. This allows the host
Packet RAM
to access data to allow the setup of the PCMCIA
ISA bus interface
multi-function card.
PCMCIA interface
EEPROM interface
In ISA mode, the serial EEPROM acts as
Encoder decoder with AUI interface
storage for configuration and IEEE Ethernet
Full duplex, magic packet 10BASE-T
address information compatible with the existing
transceiver
LAN9000 family of ISA Ethernet controllers.
Lucent Technologies and Rockwell
International modem interface
In PCMCIA mode, the serial EEPROM stores
the CIS, as well as the IEEE address, High performance:
information, but it does not store any I/O or IRQ
Chained (“back-to-back”) packet handling
information since this information is handled by
with no CPU intervention:
the host’s socket controller. For CIS
Queues transmit packets
requirements above 512 bytes, an optional
Queues receive packets
external parallel EEPROM can be used in
Full duplex operation for higher network
conjunction with the internal CIS. This allows
throughput
additional external, non-volatile storage for
Stores results in memory along with
applications that require XIP and use the
packet
modem function. If the serial EEPROM is not
Queues Ethernet and modem interrupts
used in PCMCIA mode, the parallel EEPROM
Optional single interrupt upon
must be used. In this case, the parallel
completion of transmit chain
EEPROM is selected for the first 512 bytes of
storage as well, allowing the CIS to be stored in Fast block move operation for load/unload:
the parallel EEPROM and, on power-up, to be
CPU sees packet bytes as if stored
read directly by the host. The remaining parallel
contiguously
EEPROM can be used for XIP applications, if
Handles 16 bit transfers regardless of
needed.
address alignment
Access to packet through fixed window
5
5 Page 
PIN NO.
NAME
92 Interrupt 2
nStatus
Changed
93 Interrupt 3
85 nI/O16
88 nI/O Read
87 nI/O Write
86 nMemory
Read
nOutput
Enable
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
TYPE
DESCRIPTION
nINPACK
PCMCIA - Output asserted to acknowledge
read cycles for an enabled function.
INTR2
O24 ISA - Output. Active high interrupt signal. The
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
nSTSCHG
PCMCIA - Status changed bit. Depending on
the setting of the RingEn bit (Modem CCSR),
this pin either reflects the ringing status (ExCA
mode) or the state of the Modem Changed bit.
The ringing status is obtained by stretching the
MRINGIN to convert a 20Hz toggle rate to a
constant level.
INTR3
O24 ISA - Output. Active high interrupt signal. The
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
nIOCS16
OD24
ISA - Active low output asserted in 16 bit
mode when AEN is low and A4-A15 decode to
the LAN91C95 address programmed into the
high byte of the Base Address Register.
nIOIS16
PCMCIA - Active low output asserted
whenever the LAN91C95 is in 16 bit mode,
and “Enable Function” bit in the ECOR register
is high, nREG is low and A4-A15 decode to
the LAN address specified in I/O Base
Registers 0 and 1 in PCMCIA attribute space.
nIORD
IS with
pullup
Input. Active low read strobe used to access
the LAN91C95 IO space.
nIOWR
IS with
pullup
Input. Active low write strobe used to access
the LAN91C95 IO space.
nMEMR
IS with
pullup
ISA - Active low signal used by the host
processor to read from the external ROM.
nOE PCMCIA - Output Enable input used to read
from the COR, CSR and attribute memory.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN91C95.PDF ] | |
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