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PDF LAN91C100 Data sheet ( Hoja de datos )
| Número de pieza | LAN91C100 | |
| Descripción | Fast Ethernet Controller | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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LAN91C100
ADVANCE INFORMATION
FEAST™
Fast Ethernet Controller
FEATURES
• Dual Speed CSMA/CD Engine (10 Mbps
• Built-in Transparent Arbitration for Slave
and 100 Mbps)
Sequential Access Architecture
• Compliant with IEEE 802.3 100BASE-T
• Flat MMU Architecture with Symmetric
Specification
Transmit and Receive Structures and
• Supports 100BASE-TX, 100BASE-T4, and
Queues
10BASE-T Physical Interfaces
• MII (Media Independent Interface)
• 32 Bit Wide Data Path (Into Packet Buffer
Compliant MAC-PHY Interface (Compliant
Memory)
with Emerging MII Standard Interface)
• Support for 32 and 16 Bit Buses
• MII Management Serial Interface
• Support for 32, 16 and 8 Bit CPU Accesses
• Seven Wire Interface to 10 Mbps ENDEC
• Synchronous, Asynchronous and Burst
(LAN83C694)
DMA Interface Mode Options
• EEPROM-Based Setup
• 128 Kbyte External Memory
• 208 Pin PQFP and TQFP Package
GENERAL DESCRIPTION
The LAN91C100 FEAST is a high-speed
network controller designed to facilitate the
implementation of Fast Ethernet adapters and
connectivity products. It contains a dual speed
CSMA/CD engine that implements the MAC
portion of the CSMA/CD protocol at 10 and 100
Mbps and couples it with a lean and fast data
and control path system architecture to ensure
data movement with no bottlenecks at 100
Mbps.
Memory management is handled using a unique
MMU (Memory Management Unit) architecture
and a 32-bit wide data path. This I/O mapped
architecture can sustain back-to-back frame
transmission and reception for superior data
throughput and optimal performance. It also
dynamically allocates buffer memory in an
efficient buffer utilization scheme, reducing
software tasks and relieving the host CPU from
performing these housekeeping functions. The
total memory size is 128 Kbytes (external),
equivalent to a total chip storage (transmit and
receive) of 64 outstanding packets.
FEAST provides a flexible slave interface for
easy connectivity with industry-standard buses.
The Bus Interface Unit (BIU) can handle
synchronous as well as asynchronous buses,
with different signals being used for each one.
FEAST's bus interface supports synchronous
buses like the VESA local bus, as well as burst
mode DMA for EISA environments.
Asynchronous bus support for ISA is supported
1 page  
DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS
PQFP/TQFP
PIN NO.
184
NAME
Write/nRea
d
SYMBOL
W/nR
BUFFER
TYPE
I
DESCRIPTION
Input. Defines the direction of synchronous
cycles. Write cycles when high, read cycles
when low.
181 nVL Bus nVLBUS
Access
IP Input. When low the LAN91C100
synchronous bus interface is configured for
VL Bus accesses. Otherwise the
LAN91C100 is configured for EISA DMA
burst accesses. Does not affect the
asynchronous bus interface.
105 Local Bus LCLK
Clock
I Input. Used to interface synchronous buses.
Maximum frequency is 50 MHz. Limited to
8.33 MHz for EISA DMA burst mode.
175 Asynchron- ARDY
ous Ready
OD16
Open drain output. ARDY may be used
when interfacing asynchronous buses to
extend accesses. Its rising (access
completion) edge is controlled by the XTAL1
clock and therefore asynchronous to the
host CPU or bus clock.
106 nSynchron- nSRDY
ous Ready
O16 Output. This output is used when
interfacing synchronous buses and
nVLBUS=0 to extend accesses. This signal
remains normally inactive, and its falling
edge indicates completion. This signal is
synchronous to the bus clock LCLK.
109 nReady nRDYRTN
Return
I Input. This input is used to complete
synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK edges,
and synchronous cycles are delayed until it
is sampled high.
176 Interrupt
187-189
INT0-INT3
O24 Outputs. Only one of these interrupts is
selected to be used; the other three are tri-
stated. The selection is determined by the
value of INT SEL1-0 bits in the
Configuration Register.
5
5 Page 
FUNCTION
Table 1 - LAN91C100 Pin Requirements
PIN SYMBOLS
System Address Bus
A1-A15, AEN, nBE0-nBE3
System Data Bus
D0-D31
System Control Bus
RESET, nADS, LCLK, ARDY, nRDYRTN,
nSRDY, INT0-INT3, nLDEV, nRD, nWR,
nDATACS, nCYCLE, W/nR, nVLBUS
Serial EEPROM
EEDI, EEDO, EECS, EESK, ENEEP,
IOS0-IOS2
RAM Data Bus
RD0-RD31
RAM Address Bus
RA2-RA16
RAM Control Bus
nROE, nRWE0-nRWE3, RCVDMA
Crystal Oscillator
XTAL1, XTAL2
Power
VDD, AVDD
Ground
GND, AGND
External ENDEC 10 Mbps
TXEN, TXD, CRS, COL, RXD, TXC, RXC,
LBK, nLNK, nFSTEP, AUISEL, MIISEL
Physical Interface 100 Mbps TXEN100, CRS100, COL100, RX_DV,
RX_ER, TXD0-TXD3, RXD0-RXD3, MDI,
MDO, MCLK
Clocks
TX25, RX25
Miscellaneous
RBIAS, nCSOUT
TOTAL
NUMBER OF PINS
20
32
17
8
32
15
6
2
19
21
12
16
2
2
204
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN91C100.PDF ] | |
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