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PDF LAN83C180 Data sheet ( Hoja de datos )
| Número de pieza | LAN83C180 | |
| Descripción | 10/100 Fast Ethernet PHY Transceiver | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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LAN83C180
PRELIMINARY
10/100 Fast Ethernet PHY Transceiver
FEATURES
Single Chip 100Base-TX/10Base-T Ethernet
Physical Layer (PHY) Solution
Dual Speed – 10/100 Mbps
Full MII Interface for a Glueless MAC Connection
MI Interface for Configuration and Status
Half Duplex and Full Duplex in Both 10BASE-T and
100BASE-TX
Repeater Mode
Extended Register Set
Integrated 10BASE-T Transceivers and
Receive/Transmit Filters
Integrated Adaptive Equalizer and Base Line
Wander Correction
Full Auto Negotiation Support for 10BASE-T and
100BASE-TX Both Half and Full Duplex
Parallel Detection for Supporting Non Auto
Negotiation Legacy in Link Partners
Low Current
Low Power Mode
Internal Power on Reset
Single Magnetics for 10BASE-T and 100BASE-TX
Operation for a Single RJ45 Connector
Support for IEEE-802.3x Flow Control Specification
5 Integrated Status LED Drivers
- Full Duplex
- 10/100
- Activity
- Collision
- Link
Low External Component Count
64 Pin TQFP Package (1.0 mm Body Thickness)
GENERAL DESCRIPTION
The LAN83C180 is a single chip CMOS physical layer (PHY) solution providing all necessary functions between the
Media Independent Interface (MII) and the magnetics connected to Category 5 twisted pair media. It is designed for
10BASE-T and 100BASE-TX Ethernet, and is based on the IEEE 802.3 specifications.
The LAN83C180 is compatible with the Auto Negotiation section of IEEE 802.3u and provides all the support needed
for the IEEE 802.3x Full Duplex specification. The LAN83C180 can operate in adapter mode or repeater/switch
modes.
ORDERING INFORMATION
Order Number: LAN83C180 TQFP
64 Pin TQFP Package
SMSC DS – LAN83C180
Rev. 08/24/2001
1 page  
PIN #
19
18
25
26
33
34
13
DESCRIPTION OF PIN FUNCTIONS
NAME
RXIN
RXIP
TXON
TXOP
TXREF10
TXREF100
nRESET
TYPE
DESCRIPTION
MD INTERFACE
Diff. Input Differential receive pair from magnetics (-)
Diff. Input Differential receive pair from magnetics (+)
Diff. Output 100 Differential transmit pair to magnetics (-)
Diff. Output 100 Differential transmit pair to magnetics (+)
Input 10BASE-T transmitter current setting pin
Input 100BASE-TX transmitter current setting pin
Input/
Output
Active low, power-on reset output and external reset
input.
41 XTAL1
40 XTAL2
46 MDC
45 MDIO
52
55,56,57,5
8
51
59
1
60,61,62,6
3
3
64
50
49
RX_CLK
RXD0,RXD1,RXD2,
RXD3
RX_DV
RX_ER
TX_CLK
TXD0,TXD1,TXD2,T
XD3
TX_EN
TX_ER
CRS
COL
43
22
48
21
31,30,29,1
6,12
4
REFCLK
ANEN
RXEN
RPTR
PA0,PA1,
PA2,PA3,PA4
FDST
6 SPDST
23 ICFG
7 ACTST/MINT
Input
25MHz crystal input. This signal should be pulled
high when using REFCLK.
Input
25MHz crystal input. This signal should be left
unconnected when using REFCLK.
MII INTERFACE
Input Management interface clock (up to 2.5MHz)
Input/ Management data
OUTPUT
Output Receive clock (2.5MHz for 10, 25MHz for 100)
Output Receive data MII interface
Output
Output
Output
Input
Receive data valid. Active high
Receive error. Active high. (RXD4 in symbol mode)
Transmit clock (2.5MHz for 10, 25MHz for 100)
Transmit Data MII interface
Input Transmit Enable. Active high
Input Transmit Error. Active high. (TXD4 in symbol mode)
Output Carrier sense signal. Active high
Output Collision signal. Active high
MISCELLANEOUS
Input
Reference clock. This signal should be pulled high
when using crystal.
Input Auto Negotiation enable. Active high
Input Receive enable. Active high
Input Repeater enable. Active high
Input PHY address
MISCELLANEOUS/LED
Input/ Full duplex LED status indication when nRESET
OUTPUT high. Active low. Input when nRESET is low. High
input means the LAN83C180 advertises full duplex
capability
Input Speed (10/100) LED status indication when
nRESET high. High for 100Mb/s mode. Input when
nRESET is low. Low input will cause the
LAN83C180 to advertise 100Mb/s capability.
Input Interrupt configuration. MINT on pin 8 when High,
on pin 7 when Low.
Output Receive/Transmit activity LED status indication
(Active Low) if ICFG = 1. If ICFG = 0, output is
MINT and activity is indicated on the LNKST output.
SMSC DS – LAN83C180
Page 5
Rev. 08/24/2001
5 Page 
A false CRS event happens if, at the beginning of a carrier event, the JK symbols are not received correctly.
When the LAN83C180 is in 100M mode it will count all false CRS events in register 27 bits 7:0. This counter is self
cleared upon read. If a disconnect event occurs between the consecutive reads of register 27, bit 15 in the register
will set high.
ICFG - Interrupt
The LAN83C183 offers an "MII" interrupt output which can be used to interrupt the host whenever a change in link
status occurs - this output is multiplexed onto either the ACTST or COLST pins. When ICFG is high MINT (the MII
interrupt) replaces COLST on pin 8. With ICFG low MINT is output on ACTST (pin 7) and activity is now indicated on
the LINKST pin 15 as follows:
No Link - LINKST High
Link, no Activity - LINKST Low
Link, Activity - LINKST Toggles (for flashing LED)
MINT is active low by default, but may be inverted by writing bit 12 of register 24.
MINT will be asserted whenever a change in link status occurs (loss of link/gaining link). MINT will remain asserted
until the controller acknowledges the interrupt by writing to register 21 (any data pattern will accepted).
Should one or more link status change occur between the assertion of MINT and an acknowledge then a further
interrupt will be deasserted and then reasserted (min deassertion time 100ns, max 150ns).
Only a single interrupt event may be queued at any one time. Multiple status changes between acknowledge events
will generate only a single queued interrupt.
Auto-Negotiation Enable (ANEN)
Auto-negotiation may be disabled on reset by setting the ANEN pin to logic zero. During operation, auto-negotiation
can be disabled by setting the ANEN pin low or by setting bit 12 of register 0 to zero. If auto-negotiate is disabled,
the LAN83C180 will lose the link, and link will be re-established only after the LAN83C180 control state machine has
determined the speed.
MII Management Interface
The management interface is a 2 wire serial interface connecting a PHY to a management entity. The management
unit controls the PHY and gathers information on the status of the PHY. It does this via the implemented registers.
SMSC DS – LAN83C180
Page 11
Rev. 08/24/2001
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LAN83C180.PDF ] | |
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