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PDF FDC37C93X Data sheet ( Hoja de datos )
| Número de pieza | FDC37C93X | |
| Descripción | Plug and Play Compatible Ultra I/O Controller | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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FDC37C93x
Plug and Play Compatible Ultra I/O™ Controller
FEATURES
• 5 Volt Operation
• Licensed CMOS 765B Floppy Disk
• ISA Plug-and-Play Standard (Version 1.0a)
Compatible Register Set
• 8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
• Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 1µa Standby Current (typ)
• Intelligent Auto Power Management
• 2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- 4 DMA Options
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Game Port Select Logic
- Supports Two Floppy Drives Directly
- 24 mA AT Bus Drivers
- Low Power CMOS Design
Controller Core
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- 48 mA Drivers and Schmitt Trigger
Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
• Enhanced Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
• Serial Ports
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte
FIFOs
- Programmable Baud Rate Generator
- Modem Control Circuitry Including 230K
and 460K Baud
- IrDA, HP-SIR, ASK-IR Support
• IDE Interface
- Relocatable to 480 Different Addresses
- 13 IRQ Options (IRQ Steering through
chip)
- Two Channel/Four Drive Support
- On-Chip Decode and Select Logic
Compatible with IBM PC/XT® and
PC/AT® Embedded Hard Disk Drives
• Serial EEPROM Interface
• Multi-Mode™ Parallel Port with ChiProtect™
1 page  
PIN NO.
DESCRIPTION OF PIN FUNCTIONS
NAME
SYMBOL
PROCESSOR/HOST INTERFACE
72:79 System Data Bus
SD[0:7]
41:52 System Address Bus
SA[0:11]
53 Chip Select/SA12 (Active Low)(Note 1)
nCS
70 Address Enable (DMA master has bus control) AEN
90 I/O Channel Ready
IOCHRDY
80 Reset Drive
RESET_DRV
67:61, Interrupt Requests [1,3:12,14,15]
59:54 (Polarity control for IRQ8)
IRQ[1,3:12,
14,15]
82,84, DMA Requests
86,88
DRQ[0:3]
81,83, DMA Acknowledge
85,87
nDACK[0:3]
89 Terminal Count
TC
68 I/O Read
nIOR
69 I/O Write
nIOW
35 Serial Clock Out (24 MHz)
24CLK
36 16 MHz Out
16CLK
22 14.318MHz Clock Input
CLOCKI
37 14.318MHz Clock Output 1
CLKO1
38 14.318MHz Clock Output 2
CLKO2
39 14.318MHz Clock Output 3
CLKO3
POWER PINS
21, 60, +5V Supply Voltage
101, 125,
139
VCC
1, 8, 40, Ground
71, 95,
123, 130
GND
FDD INTERFACE
17 Read Disk Data
nRDATA
12 Write Gate
nWGATE
11 Write Disk Data
nWDATA
BUFFER TYPE
I/O24
I
I
I
OD24
IS
OD24
O24
I
I
I
I
08SR
08SR
ICLK
O16SR
08SR
08SR
IS
OD48
OD48
5
5 Page 
FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, IDE, serial and
parallel ports can be moved via the
configuration registers. Some addresses are
used to access more than one register.
The host processor communicates with the
FDC37C93x through a series of read/write
registers. The port addresses for these registers
are shown in Table 1. Register access is
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide except
the IDE data register at port 1F0H which is 16
bits wide. All host interface output buffers are
capable of sinking a minimum of 12 mA.
Table 1 - Super I/O Block Addresses
LOGICAL
ADDRESS
BLOCK NAME
DEVICE
Base+(0-5) and +(7)
Floppy Disk
0
Base+(0-7)
Serial Port Com 1
4
Base+(0-7)
Serial Port Com 2
5
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
3
Base1+(0-7), Base2+(0)
IDE 1
1
Base1+(0-7), Base2+(0)
IDE 2
2
NOTES
IR Support
Note 1: Refer to the configuration register descriptions for setting the base address
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FDC37C93X.PDF ] | |
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