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PDF CA1524 Data sheet ( Hoja de datos )

Número de pieza CA1524
Descripción Regulating Pulse Width Modulator
Fabricantes Intersil Corporation 
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No Preview Available ! CA1524 Hoja de datos, Descripción, Manual

October 2000
CA2524 IPSRAONDOUCBTSOLETE
CA1524, CA2524
CA3524
Regulating Pulse Width Modulator
Features
Description
• Complete PWM Power Control Circuitry
• Separate Outputs for Single-Ended or Push-Pull
Operation
• Line and Load Regulation . . . . . . . . . . . . . . . 0.2% (Typ)
• Internal Reference Supply with 1% (Max) Oscillator
and Reference Voltage Variation Over Full
Temperature Range
• Standby Current of Less Than 10mA
• Frequency of Operation Beyond 100kHz
• Variable-Output Dead Time of 0.5µs to 5µs
• Low VCE(sat) Over the Temperature Range
Applications
• Positive and Negative Regulated Supplies
• Dual-Output Regulators
• Flyback Converters
• DC-DC Transformer-Coupled Regulating Converters
• Single-Ended DC-DC Converters
• Variable Power Supplies
The CA1524 and CA3524 are silicon monolithic integrated
circuits designed to provide all the control circuitry for use in
a broad range of switching regulator circuits.
The CA1524 and CA3524 have all the features of the indus-
try types SG1524, SG2524, and SG3524, respectively. A
block diagram of the CA1524 series is shown in Figure 1.
The circuit includes a zener voltage reference, transconduc-
tance error amplifier, precision R-C oscillator, pulse-width
modulator, pulse-steering flip-flop, dual alternating output
switches, and current-limiting and shutdown circuitry. This
device can be used for switching regulators of either polarity,
transformer-coupled dc-dc converter, transformerless volt-
age doublers, dc-ac power inverters, highly efficient variable
power supplies, and polarity converter, as well as other
power-control applications.
Ordering Information
PART
NUMBER
CA1524E
CA1524F
CA2524E
CA2524F
CA3524E
CA3524F
TEMPERATURE
RANGE
PACKAGE
-55oC to +125oC 16 Lead Plastic DIP
-55oC to +125oC 16 Lead CerDIP
0oC to +70oC 16 Lead Plastic DIP
0oC to +70oC 16 Lead CerDIP
0oC to +70oC 16 Lead Plastic DIP
0oC to +70oC 16 Lead CerDIP
Pinout
CA1524, CA3524
(PDIP, CERDIP)
TOP VIEW
INV. INPUT
NON-
INV. INPUT
OSC OUT
(+) C.L.
SENSE
(-) C.L.
SENSE
RT
1
2
3
4
5
6
CT 7
GND 8
16 VREF
15 V+
14 EMITTER B
13 COLLECTOR B
12 COLLECTOR A
11 EMITTER A
10 SHUTDOWN
9 COMPENSATION
AND COMPARATOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
1
File Number 1239.4

1 page




CA1524 pdf
CA1524, CA2524, CA3524
Schematic Diagram
15 VIN
8
GND
Q1
D1
R1
500
Q2
R5
1K
Q7
Q6
R7
1K
Q13
Q3 Q4
R2
2.7K
R3
6.3K
RC
10K
Q9 C1
20pF
Q10
Q11
D2
RA
5.3K
QA
RB
4.8K Q5
R4
500
Q12
R6
500
Q17
Q18
R12
10K
Q16
R11
500 R13
RD 6
R16
16.2K
10K 1.9K
R14
450
Q19
C4
R17 R18
18.7 18.7
KK
R8
8.4K
PULSE
STEERING
FLIP-FLOP
Q21
Q23
R19 R18
18.7 18.7
KK
C2
20pF
Q14
Q15
N+ P
Q20
Q22
Q24
R9 R10
500 1K
R15
25K
Q42 Q43 Q47
OSC SECTION
Q48
R43
7.4K
ERROR
AMP
Q59 Q60
A
B
16
VREF
+5V
C
D
E
F
G
H
I
6 Q44
RT
Q49 Q50
Q55
INV.
IN
1
Q56 Q57
Q61
2
NON-INV.
INPUT
J
R44
7 1.8K
CT Q51
Q58 Q62
Q46
Q45 R41
24K
Q52
OSC.
OUT
3
R39 R40 R42
1K 560 19.8K
R45
25K
Q53
Q54
R47 R48
1K 2K
R46
3.3K
K
L
5

5 Page





CA1524 arduino
CA1524, CA2524, CA3524
Applications (Note 1)
A capacitor-diode output filter is used in Figure 19 to convert
+15VDC to -5VDC at output currents up to 50mA. Since the
output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage.
Capacitor-Diode Output Circuit
A capacitor-diode output filter is used in Figure18 to convert
+15VDC to -5VDC at output currents up to 50mA. Since the
output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage range of -0.5V to -20V with an output
current of 40mA.
Single-Ended Switching Regulator
The CA1524 in the circuit of Figure 19 has both output
stages connected in parallel to produce an effective 0% -
90% duty cycle. Transistor Q1 is pulsed on and off by these
output stages. Regulation is achieved from the feedback
provided by R1 and R2 to the error amplifier which adjusts
the on-time of the output transistors according to the load
current being drawn. Various output voltages can be
obtained by adjusting R1 and R2. The use of an output
inductor requires an R-C phase compensation network to
stabilize the system. Current limiting is set at 1.9 amperes by
the sense resistor R3.
NOTE:
1. For additional information on the application of this device and a
further explanation of the circuits below, see Intersil Application
Note AN6915 “Application of the CA1524 series PWM lC”.
V+
+15V
5K
R2
15K
1
5K
0.1µF
2K
R1 21
5K
116
61
0.01µF
71
31
110
61
CA3524
18
112
IN4001
111
20µF
113
IN4001
114
41
IN4001
15
19
0.01µF
-5V
20mA
50µF
R1 = 5K
R2 = R1 ( | VO | + 2.5)
(VREF - 2.5)
FIGURE 18. CAPACITOR-DIODE OUTPUT CIRCUIT
V+
+28V
R2
5K
R1
5K
5K
0.1µF
5K
3K
0.02µF
1
21
116
61
71
31
110
V-
115
CA3524
18
2N6388
112
111
2K
113
114
41
15
19
0.001µF
50K
Q1
0.9mH
+5V IA
500µF
RURD410
0.1
FIGURE 19. SINGLE-ENDED LC SWITCHING REGULATOR CIRCUIT
11

11 Page







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