PDF SCANPSC110F Data sheet ( Hoja de datos )

Número de pieza	SCANPSC110F
Descripción	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
Fabricantes	Fairchild Semiconductor
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No Preview Available ! March 1993 Revised August 2000 SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) General Description The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advan- tage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or combined serially. Addressing is accomplished by load- ing the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruc- tion. The 32-bit TCK counter enables built in self test oper- ations to be performed on one port while other scan chains are simultaneously tested. Features s True IEEE1149.1 hierarchical and multidrop addressable capability s The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses s 3 IEEE 1149.1-compatible configurable local scan ports s Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three s 32-bit TCK counter s 16-bit LFSR Signature Compactor s L4 s local TAPs can be 3-stated via the OE input to allow an alternate test master to take control of the local TAPs Ordering Code: Order Number Package Number Package Description SCANPSC110FSC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description TCKB TMSB TDIB TDOB TRST Backplane Test Clock Input Backplane Test Mode Select Input Backplane Test Data Input Backplane Test Data Output Asynchronous Test Reset Input (Active LOW) S(0,5) OE Address Select Port Local Scan Port Output Enable (Active LOW) TCKL(1–3) Local Port Test Clock Output TMSL(1–3) Local Port Test Mode Select Output TDIL(1–3) Local Port Test Data Input TDOL(1–3) Local Port Test Data Output © 2000 Fairchild Semiconductor Corporation DS011570 www.fairchildsemi.com 1 page Overview of SCANPSC110F Bridge Functions (Continued) FIGURE 2. SCANPSC110F Bridge State Machines The SCANPSC110F contains three distinct but coupled state-machines (see Figure 2). The first of these is the TAP-control state-machine, which is used to drive the SCANPSC110Fs scan ports in conformance with the 1149.1 Standard (see Figure 17 of appendix). The second is the SCANPSC110F-selection state-machine (Figure 3). The third state-machine actually consists of three identical but independent state-machines (see Figure 4), one per SCANPSC110F local scan port. Each of these scan port- selection state-machines allows individual local ports to be inserted into and removed from the SCANPSC110Fs over- all scan chain. The SCANPSC110F selection state-machine performs the address matching which gives the SCANPSC110F its multi-drop capability. That logic supports single- SCANPSC110F access, multi-cast, and broadcast. The SCANPSC110F-selection state-machine implements the chip’s Level-1 protocol. KEY + = OR & = AND ADDR = 6-bit address in the Instruction Register SLOT = Static address in the SCANPSC110F Selection Controller FIGURE 3. State Machine for SCANPSC110F Bridge Selection Controller 5 www.fairchildsemi.com 5 Page Level 2 Protocol (Continued) along with any other yet undefined Op-Codes, will cause the device identification register to be inserted into the active scan chain. LEVEL 2 INSTRUCTION DESCRIPTIONS BYPASS: The BYPASS instruction selects the bypass reg- ister for insertion into the active scan chain when the SCANPSC110F is selected. EXTEST: The EXTEST instruction selects the boundary- scan register for insertion into the active scan chain. The boundary-scan register consists of seven “sample only” shift cells connected to the S(0–5) and OE inputs. On the SCANPSC110F, the EXTEST instruction performs the same function as the SAMPLE/PRELOAD instruction, since there aren’t any scannable outputs on the device. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruc- tion selects the boundary-scan register for insertion into the active scan chain. The boundary-scan register consists of seven “sample only” shift cells connected to the S(0–5) and OE inputs. IDCODE: The IDCODE instruction selects the device iden- tification register for insertion into the active scan chain. When IDCODE is the current active instruction the device identification “0FC0E01F” Hex is captured upon exiting the Capture-DR state. TABLE 5. Level 2 Protocol and Op-Codes Instructions BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT* MODESEL MCGRSEL SOFTRESET LFSRSEL LFSRON LFSROFF CNTRSEL CNTRON CNTROFF Other Undefined Hex Op-Code FF 00 81 AA E7 C5 84 C6 C3 8E 03 88 C9 0C 8D CE 0F 90 TBD Binary Op-Code 11111111 00000000 10000001 10101010 11100111 11000101 10000100 11000110 11000011 10001110 00000011 10001000 11001001 00001100 10001101 11001110 00001111 10010000 TBD Data Register Bypass Register Boundary-Scan Register Boundary-Scan Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Mode Register Multi-Cast Group Register Device Identification Register Linear Feedback Shift Register Device Identification Register Device Identification Register 32-Bit TCK Counter Register Device Identification Register Device Identification Register Device Identification Register Note 4: All other instructions act on selected SCANPSC110Fs only. UNPARK: This instruction unparks the Local Scan Port Network and inserts it into the active scan chain as config- ured by the Mode register (see Table 4). Unparked LSPs are sequenced synchronously with the SCANPSC110F's TAP controller. When a LSP has been parked in the Test-Logic-Reset or Run-Test/Idle state, it will not become unparked until the SCANPSC110F's TAP Controller enters the Run-Test/Idle state following the UNPARK instruction. If an LSP has been parked in one of the stable pause states (Pause-DR or Pause-IR), it will not become unparked until the SCANPSC110F's TAP Controller enters the respective pause state. (See Figures 9, 10, 11, 12). PARKTLR: This instruction causes all unparked LSPs to be parked in the Test-Logic-Reset TAP controller state and removes the LSP network from the active scan chain. The LSP controllers keep the LSPs parked in the Test-Logic- Reset state by forcing their respective TMSL output with a constant logic “1” while the LSP controller is in the Parked- TLR state (see Figure 4). PARKRTI: This instruction causes all unparked LSPs to be parked in the Run-Test/Idle state. When a LSPn is active (unparked), its TMSL signals follow TMSB and the LSPn controller state transitions are synchronized with the TAP Controller state transitions of the SCANPSC110F. When the instruction register is updated with the PARKRTI instruction, TMSLwill be forced to a constant logic “0”, causing the unparked local TAP Controllers to be parked in the Run-Test/Idle state. When an LSPn is parked, it is removed from the active scan chain. PARKPAUSE: The PARKPAUSE instruction has dual func- tionality. It can be used to park unparked LSPs or to unpark parked LSPs. The instruction places all unparked LSPs in one of the TAP Controller pause states. A local port does not become parked until the SCANPSC110F's TAP Con- troller is sequenced through Exit1-DR/IR into the Update- DR/IR state. When the SCANPSC110F TAP Controller is in the Exit1-DR or Exit1-IR state and TMSB is HIGH, the LSP controller forces a constant logic '0” onto TMSL thereby parking the port in the Pause-DR or Pause-IR state respec- tively (see Figure 4 ). Another instruction can then be loaded to reconfigure the local ports or to deselect the SCANPSC110F (i.e., MODESEL, GOTOWAIT, etc.). 11 www.fairchildsemi.com 11 Page

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