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PDF SCAN18245T Data sheet ( Hoja de datos )
| Número de pieza | SCAN18245T | |
| Descripción | Non-Inverting Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1991
Revised May 2000
SCAN18245T
Non-Inverting Transceiver with 3-STATE Outputs
General Description
The SCAN18245T is a high speed, low-power bidirectional
line driver featuring separate data inputs organized into
dual 9-bit bytes with byte-oriented output enable and direc-
tion control signals. This device is compliant with IEEE
1149.1 Standard Test Access Port and Boundary Scan
Architecture with the incorporation of the defined boundary-
scan test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select (TMS),
and Test Clock (TCK).
Features
s IEEE 1149.1 (JTAG) Compliant
s Dual output enable control signals
s 3-STATE outputs for bus-oriented applications
s 9-bit data busses for parity applications
s Reduced-swing outputs source 32 mA/sink 64 mA
s Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
s TTL compatible inputs
s 25 mil pitch SSOP (Shrink Small Outline Package)
s Includes CLAMP and HIGHZ instructions
s Member of Fairchild’s SCAN Products
Ordering Code:
Order Number Package Number
Package Description
SCAN18245TSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
A1(0–8)
B1(0–8)
A2(0–8)
B2(0–8)
G1, G2
Side A1 Inputs or 3-STATE Outputs
Side B1 Inputs or 3-STATE Outputs
Side A2 Inputs or 3-STATE Outputs
Side B2 Inputs or 3-STATE Outputs
Output Enable Pins
DIR1, DIR2 Direction of Data Flow Pins
© 2000 Fairchild Semiconductor Corporation DS010961
www.fairchildsemi.com
1 page  
Boundary-Scan Register Definition Index
Bit No. Pin Name Pin No. Pin Type Scan Cell Type
79 DIR1 3 Input TYPE1
78 G1 54 Input TYPE1
77 AOE1
Internal TYPE2
76 BOE1
Internal TYPE2 Control
75 DIR2 26 Input TYPE1 Signals
74 G2 31 Input TYPE1
73 AOE2
Internal TYPE2
72 BOE2
Internal TYPE2
71 A10 55 Input TYPE1
70 A11 53 Input TYPE1
69 A12 52 Input TYPE1
68 A13 50 Input TYPE1
67 A14 49 Input TYPE1 A1–in
66 A15 47 Input TYPE1
65 A16 46 Input TYPE1
64 A17 44 Input TYPE1
63 A18 43 Input TYPE1
62 A20 42 Input TYPE1
61 A21 41 Input TYPE1
60 A22 39 Input TYPE1
59 A23 38 Input TYPE1
58 A24 36 Input TYPE1 A2–in
57 A25 35 Input TYPE1
56 A26 33 Input TYPE1
55 A27 32 Input TYPE1
54 A28 30 Input TYPE1
53 B10
2 Output TYPE2
52 B11
4 Output TYPE2
51 B12
5 Output TYPE2
50 B13
7 Output TYPE2
49 B14
8 Output TYPE2 B1–out
48 B15 10 Output TYPE2
47 B16
11 Output TYPE2
46 B17 13 Output TYPE2
45 B18 14 Output TYPE2
44 B20 15 Output TYPE2
43 B21 16 Output TYPE2
42 B22 18 Output TYPE2
41 B23 19 Output TYPE2
40 B24 21 Output TYPE2 B2–out
39 B25 22 Output TYPE2
38 B26 24 Output TYPE2
37 B27 25 Output TYPE2
36 B28 27 Output TYPE2
Bit No. Pin Name Pin No. Pin Type Scan Cell Type
35 B10
2 Input TYPE1
34 B11
4 Input TYPE1
33 B12
5 Input TYPE1
32 B13
7 Input TYPE1
31 B14
8 Input TYPE1 B1–in
30 B15 10 Input TYPE1
29 B16
11 Input TYPE1
28 B17 13 Input TYPE1
27 B18 14 Input TYPE1
26 B20 15 Input TYPE1
25 B21 16 Input TYPE1
24 B22 18 Input TYPE1
23 B23 19 Input TYPE1
22 B24 21 Input TYPE1 B2–in
21 B25 22 Input TYPE1
20 B26 24 Input TYPE1
19 B27 25 Input TYPE1
18 B28 27 Input TYPE1
17 A10 55 Output TYPE2
16 A11 53 Output TYPE2
15 A12 52 Output TYPE2
14 A13 50 Output TYPE2
13 A14 49 Output TYPE2 A1–out
12 A15 47 Output TYPE2
11 A16 46 Output TYPE2
10 A17 44 Output TYPE2
9 A18 43 Output TYPE2
8 A20 42 Output TYPE2
7 A21 41 Output TYPE2
6 A22 39 Output TYPE2
5 A23 38 Output TYPE2
4 A24 36 Output TYPE2 A2–out
3 A25 35 Output TYPE2
2 A26 33 Output TYPE2
1 A27 32 Output TYPE2
0 A28 30 Output TYPE2
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11 www.fairchildsemi.com
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet SCAN18245T.PDF ] | |
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