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PDF SCAN182245A Data sheet ( Hoja de datos )
| Número de pieza | SCAN182245A | |
| Descripción | Non-Inverting Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 1996
SCAN182245A
Non-Inverting Transceiver with
25X Series Resistor Outputs
General Description
The SCAN182245A is a high performance BiCMOS bidirec-
tional line driver featuring separate data inputs organized
into dual 9-bit bytes with byte-oriented output enable and
direction control signals This device is compliant with
IEEE 1149 1 Standard Test Access Port and Boundary
Scan Architecture with the incorporation of the defined
boundary-scan test logic and test access port consisting of
Test Data Input (TDI) Test Data Out (TDO) Test Mode Se-
lect (TMS) and Test Clock (TCK)
Features
Y High performance BiCMOS technology
Y 25X series resistors in outputs eliminate the need for
external terminating resistors
Y Dual output enable control signals
Y TRI-STATE outputs for bus-oriented applications
Y 25 mil pitch SSOP (Shrink Small Outline Package)
Y IEEE 1149 1 (JTAG) Compliant
Y Includes CLAMP IDCODE and HIGHZ instructions
Y Additional instructions SAMPLE-IN SAMPLE-OUT and
EXTEST-OUT
Y Power Up TRI-STATE for hot insert
Y Member of National’s SCAN Products
Connection Diagram
Pin Names
A1(0 – 8)
B1(0 – 8)
A2(0 – 8)
B2(0 – 8)
G1 G2
DIR1 DIR2
Description
Side A1 Inputs or TRI-STATE Outputs
Side B1 Inputs or TRI-STATE Outputs
Side A2 Inputs or TRI-STATE Outputs
Side B2 Inputs or TRI-STATE Outputs
Output Enable Pins (Active Low)
Direction of Data Flow Pins
Order Number
SCAN182245ASSC
SCAN182245ASSCX
SCAN182245AFMQB
Description
SSOP in Tubes
SSOP Tape and Reel
Flatpak Military
TL F 11657 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 11657
RRD-B30M36 Printed in U S A
http www national com
1 page  
Description of BOUNDARY-SCAN Circuitry (Continued)
Scan Cell TYPE1
Scan Cell TYPE2
TL F 11657 – 11
TL F 11657 – 12
5 http www national com
5 Page 
SCAN ABT Live Insertion and Power Cycling Characteristics
SCAN ABT is intended to serve in Live Insertion backplane
applications It provides 2nd Level Isolation1 which indicates
that while external circuitry to control the output enable pin
is unnecessary there may be a need to implement differen-
tial length backplane connector pins for VCC and GND As
well pre-bias circuitry for backplane pins may be necessary
to avoid capacitive loading effects during live insertion
SCAN ABT provides control of output enable pins during
power cycling via the circuit in Figure A It essentially con-
trols the Gn pin until VCC reaches a known level
During power-up when VCC ramps through the 0 0V to 0 7V
range all internal device circuitry is inactive leaving output
and I O pins of the device in high impedance From approxi-
mately 0 8V to 1 8V VCC the Power-On-Reset circuitry
(POR) in Figure A becomes active and maintains device
high impedance mode The POR does this by providing a
low from its output that resets the flip-flop The output Q of
the flip-flop then goes high and disables the NOR gate from
an incidental low input on the Gn pin After 1 8V VCC the
POR circuitry becomes inactive and ceases to control the
flip-flop To bring the device out of high impedance the Gn
input must receive an inactive-to-active transition a high-to-
low transition on Gn in this case to change the state of the
flip-flop With a low on the Q output of the flip-flop the NOR
gate is free to allow propagation of a Gn signal
During power-down the Power-On-Reset circuitry will be-
come active and reset the flip-flop at approximately 1 8V
VCC Again the Q output of the flip-flop returns to a high and
disables the NOR gate from inputs from the Gn pin The
device will then remain in high impedance for the remaining
ramp down from 1 8V to 0 0V VCC
Some suggestions to help the designer with live insertion
issues
The Gn pin can float during power-up until the Power-On-
Reset circuitry becomes inactive
The Gn pin can float on power-down only after the Pow-
er-On-Reset has become active
The description of the functionality of the Power-On-Reset
circuitry can best be described in the diagram of Figure B
FIGURE A
TL F 11657 – 19
FIGURE B
1Section 7 ‘‘Design Consideration for Fault Tolerant Backplanes’’ Application Note AN-881
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices
11
TL F 11657 – 20
http www national com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SCAN182245A.PDF ] | |
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