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Número de pieza | CEU71A3 | |
Descripción | N-Channel Logic Level Enhancement Mode Field Effect Transistor | |
Fabricantes | CET | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CEU71A3 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas | ||
No Preview Available ! CED71A3/CEU71A3
Dec. 2002
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
30V , 65A , RDS(ON)=10mΩ @VGS=10V.
RDS(ON)=14mΩ @VGS=5.0V.
Super high dense cell design for extremely low RDS(ON).
D
High power and current handling capability.
TO-252 & TO-251 package.
G
D
G
S
CEU SERIES
TO-252AA(D-PAK)
G
DS
CED SERIES
TO-251(l-PAK)
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
VDS
VGS
ID
IDM
IS
PD
TJ, TSTG
Limit
30
Ć20
65
100
65
69
0.56
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
6
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
RįJC
RįJA
6-67
1.8
40
C/W
C/W
1 page CED71A3/CEU71A3
4
VDD
RL
VIN
D VOUT
VGS
RGEN G
S
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
6
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
10 0
D=0.5
0.2
10-1 0.1
0.05
0.02
10-2 0.01
10-3
10-4
Single Pulse
10-3
10-2
10-1
10 0
Square Wave Pulse Duration (sec)
PDM
t1
t2
1. RįJA (t)=r (t) * RįJA
2. RįJA=See Datasheet
3. TJM-TA = P* RįJA (t)
4. Duty Cycle, D=t1/t2
1
10
Figure 13. Normalized Thermal Transient Impedance Curve
10 2
6-71
5 Page |
Páginas | Total 5 Páginas | |
PDF Descargar | [ Datasheet CEU71A3.PDF ] |
Número de pieza | Descripción | Fabricantes |
CEU71A3 | N-Channel Logic Level Enhancement Mode Field Effect Transistor | CET |
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