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PDF CED02N6 Data sheet ( Hoja de datos )

Número de pieza CED02N6
Descripción N-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricantes CET 
Logotipo CET Logotipo



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No Preview Available ! CED02N6 Hoja de datos, Descripción, Manual

CED02N6/CEU02N6
Dec. 2002
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
600V , 1.9A , RDS(ON)=5@VGS=10V.
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-251 & TO-252 package.
D
G
S
CEU SERIES
TO-252AA(D-PAK)
G
DS
CED SERIES
TO-251(l-PAK)
G
D
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
Drain Current-Continuous (Tc=25 C)
-Continuous (Tc=100 C)
-Pulsed
Drain-Source Diode Forward Current
VGS
ID
ID
IDM
IS
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperautre Range
PD
TJ, TSTG
Limit
600
Ć30
1.9
1.2
6
6
43
0.34
-55 to 150
Unit
V
V
A
A
A
A
W
W/ C
C
6
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
RįJC
RįJA
2.9
50
C/W
C/W
6-77

1 page




CED02N6 pdf
CED02N6/CEU02N6
15
VDS=480V
12 ID=2A
9
6
3
0
0 6 12 18 24
Qg, Total Gate Charge (nC)
Figure 9. Gate Charge
VDD
RL
VIN
D VOUT
VGS
RGEN G
S
10
1 RDS(ON) Limit
100ijs
1ms
10ms
DC
0.1
TC=25C
Tj=25 C
0.01 Single Pulse
1 10
100 500 1000
VDS, Drain-Source Voltage (V)
Figure 10. Maximum Safe
Operating Area
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
2
1
D=0.5
0.2
0.1
0.1 0.05
0.02
0.01
Single Pulse
0.01
0.01
0.1
1 10 100
Square Wave Pulse Duration (msec)
PDM
t1
t2
1. RįJC (t)=r (t) * RįJC
2. RįJC=See Datasheet
3. TJM-TC = P* RįJC (t)
4. Duty Cycle, D=t1/t2
1000
10000
Figure 13. Normalized Thermal Transient Impedance Curve
6
6-81

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