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PDF FAN7842 Data sheet ( Hoja de datos )

Número de pieza FAN7842
Descripción High and Low Side Gate Driver
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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FAN7842
High and Low Side Gate Driver
February 2007
Features
„ Floating Channels Designed for Bootstrap Operation
to +200V
„ Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability for Both Channels
„ Common-Mode dv/dt Noise Canceling Circuit
„ Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VCC=VBS=15V
„ VCC & VBS Supply Range from 10V to 20V
„ UVLO Functions for Both Channels
„ TTL-Compatible Input Logic Threshold Levels
„ Matched Propagation Delay Below 50ns
„ Output In-phase with Input Signal
Applications
„ Half- and Full-Bridge Converters
„ Current-Fed Push-Pull Converters
„ Synchronous Buck Converters
Description
The FAN7842, a monolithic high and low side gate drive
IC, which can drive MOSFETs and IGBTs that operate up
to +200V.
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of the
high-side driver under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS=-9.8V (typical) for VBS=15V.
The input logic level is compatible with standard TTL-
series logic gates.
The UVLO circuits for both channels prevent malfunction
when VCC and VBS are lower than the specified thresh-
old voltage. Output driver current (source/sink) is typi-
cally 350mA/650mA, respectively.
8-SOP
Ordering Information
Part Number
FAN7842M(1)
FAN7842MX(1)
Operating Temp.
Range
-40°C to +125°C
Pb-Free
Yes
Note:
1. These devices passed wave soldering test by JESD22A-111.
Package
8-SOP
Packing Method
Tube
Tape & Reel
© 2006 Fairchild Semiconductor Corporation
FAN7842 Rev. 1.0.2
www.fairchildsemi.com

1 page




FAN7842 pdf
Electrical Characteristics
VBIAS (VCC, VBS) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to COM.
The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO
Symbol
Parameter
Condition
Min. Typ. Max. Unit
VCCUV+ VCC and VBS supply under voltage
VBSUV+ positive going threshold
8.2 9.2 10.0
VCCUV- VCC and VBS supply under voltage
VBSUV- negative going threshold
7.6 8.7 9.6 V
VCCUVH VCC supply under voltage lockout
VBSUVH hysteresis
0.6
ILK Offset supply leakage current
VB=VS=200V
10
IQBS Quiescent VBS supply current
VIN=0V or 5V
45 120 µA
IQCC Quiescent VCC supply current
VIN=0V or 5V
70 180
IPBS
IPCC
Operating VBS supply current
Operating VCC supply current
fIN=20kHz, rms value
fIN=20kHz, rms value
600
µA
600
VIH Logic "1" input voltage
2.9
VIL Logic "0" input voltage
VOH
High level output voltage,
VBIAS-VO
VOL Low level output voltage, VO
IO=20mA
0.8
V
1.0
0.6
IIN+ Logic "1" input bias current
IIN- Logic "0" input bias current
VIN=5V
VIN=0V
10 20
µA
1.0 2.0
IO+ Output high short circuit pulse current VO=0V, VIN=5V with PW<10µs 250 350
IO- Output low short circuit pulsed current VO=15V, VIN=0V with PW<10µs 500 650
mA
VS
Allowable negative VS pin voltage for
HIN signal propagation to HO
-9.8 -7.0 V
Dynamic Electrical Characteristics
VBIAS (VCC, VBS)=15.0V, VS=COM, CL=1000pF, and TA=25°C, unless otherwise specified.
Symbol
ton
toff
tr
tf
MT
Parameter
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Delay matching, HS & LS turn-on/off
Conditions
VS=0V
VS=0V or 200V(5)
Min.
100
100
20
Note:
5. This parameter guaranteed by design.
Typ.
170
200
60
30
Max.
300
300
140
80
50
Unit
ns
© 2006 Fairchild Semiconductor Corporation
FAN7842 Rev. 1.0.2
5
www.fairchildsemi.com

5 Page





FAN7842 arduino
Applications Information
15V 15V
100nF 10uF
HIN
LIN
1 VCC
4 COM
2 HIN
3 LIN
VB 8
VS 6
HO 7
10uF 100nF
1nF
LO 5
1nF
FAN7842 Rev.01
Figure 32. Switching Time Test Circuit
HIN
LIN
HO
LO
Figure 33. Input / Output Timing Diagram
HIN
LIN
50%
ton : Turn-on DelayTime
toff : Turn-off DelayTime
tr : Turn-on Rise Time
50%
tf : Turn-off Fall Time
ton tr
to f f tf
90%
HO
LO
10%
90%
10%
Figure 34. Switching Time Waveform Definitions
HIN 50%
LIN
LO
HO
10%
ton-L ton-H
MT
50%
toff - L
MT
toff - H
90%
LO HO
Figure 35. Delay Matching Waveform Definition
© 2006 Fairchild Semiconductor Corporation
FAN7842 Rev. 1.0.2
11
www.fairchildsemi.com

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