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PDF FMS6243 Data sheet ( Hoja de datos )

Número de pieza FMS6243
Descripción SD Video Filter Drivers
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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FMS6243
Low-Cost, 3-Channel, SD Video Filter Drivers with
External Delay Control
March 2007
Features
Three Fourth-Order 8MHz (SD) Filters
External Delay Control
Transparent Input Clamping
Dual-Video Load Drive (2Vpp, 75Ω)
AC- or DC-Coupled Inputs
AC- or DC-Coupled Outputs
DC-Coupled Outputs Eliminate AC-Coupling
Capacitors
5V Only
Lead-Free Package: TSSOP-14
Applications
Cable Set-Top Boxes
Satellite Set-Top Boxes
DVD Players
HDTV
Personal Video Recorders (PVR)
Video On Demand (VOD)
Description
The FMS6243 Low-Cost Video Filter (LCVF) is intended
to replace passive LC filters and drivers with a low-cost
integrated device. Three fourth-order filters provide
improved image quality compared to typical second- or
third-order passive solutions.
The FMS6243 can be directly driven by a DC-coupled
DAC output or an AC-coupled signal. Internal diode
clamps and bias circuitry can be used if AC-coupled
inputs are required (see the Applications section for
details).
Delay for each channel can be independently controlled
with an external capacitor.
The outputs can drive AC- or DC-coupled single (150Ω)
or dual (75Ω) loads. DC coupling the outputs removes
the need for output coupling capacitors. The input DC
levels are offset approximately +280mV at the output
(seewww.DataSheet4U.com the Applications section for details).
Ordering Information
Part Number
Package
FMS6243MTC14 14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide
FMS6243MTC14X 14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide
Pb-
Free
Yes
Yes
Operating
Temperature
Range Packing Method
-40°C to 85°C
Tube
-40°C to 85°C Tape and Reel
IN1
Del1
IN2
Del2
IN3
Del3
Transparent Clamp
2X
Transparent Clamp
2X
Transparent Clamp
2X
8MHz, 4th-order
Figure 1. Functional Block Diagram
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
OUT1
OUT2
OUT3
www.fairchildsemi.com

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FMS6243 pdf
Application Information
The FMS6243 Low-Cost Video Filter (LCVF) provides
6dB gain from input to output. In addition, the input is
slightly offset to optimize the output driver performance.
The offset is held to the minimum required value to
decrease the standing DC current into the load. Typical
voltage levels are shown in the diagram below:
I/O Configurations
For DC-coupled DAC drive with DC-coupled outputs, use
this configuration:
Figure 5. DC-Coupled Inputs and Outputs
Alternatively, if the DAC’s average DC output level
causes the signal to exceed the range of 0V to 1.4V, it
can be AC-coupled as follows:
Figure 3. Typical Voltage Levels
The FMS6243 provides an internal diode clamp to sup-
port AC-coupled input signals. If the input signal does not
go below ground, the input clamp does not operate. This
allows DAC outputs to directly drive the FMS6243 without
an AC coupling capacitor. When the input is AC-coupled,
the diode clamp sets the sync tip (or lowest voltage) just
below ground. The worst-case sync tip compression due
to the clamp can not exceed 7mV. The input level set by
the clamp combined with the internal DC offset keeps the
output within its acceptable range.
For symmetric signals like Chroma, U, V, Pb, and Pr, the
average DC bias is fairly constant and the inputs can be
AC-coupled with the addition of a pull-up resistor to set
the DC input voltage. DAC outputs can also drive these
signals without the AC-coupling capacitor. A conceptual
illustration of the input clamp circuit is shown below:
Figure 6. AC-Coupled Inputs, DC-Coupled Outputs
When driven by an unknown external source or a
SCART switch with its own clamping circuitry, the inputs
should be AC-coupled like this:
Figure 7. SCART with DC-Coupled Outputs
The same method can be used for biased signals with
the addition of a pull-up resistor to make sure the clamp
never operates. The internal pull-down resistance is
800kΩ ±20% so the external resistance should be
7.5MΩ to set the DC level to 500mV.
Figure 4. Input Clamp Circuit
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
Figure 8. Biased SCART with DC-Coupled Outputs
www.fairchildsemi.com
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