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PDF FIN24AC Data sheet ( Hoja de datos )

Número de pieza FIN24AC
Descripción USerDesTM 22-Bit Bi-Directional Serializer/Deserializer
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FIN24AC Hoja de datos, Descripción, Manual

FIN24AC
PSerDes¥
22-Bit Bi-Directional Serializer/Deserializer
September 2005
Revised December 2005
General Description
Features
The FIN24AC PSerDes¥ is a low power Serializer/Deserializer O Low power for minimum impact on battery life
(SerDes) that can help minimize the cost and power of transfer-
• Multiple power-down modes
ring wide signal paths. Through the use of serialization, the
• AC coupling with DC balance
number of signals transferred from one point to another can be
significantly reduced. Typical reduction is 4:1 to 6:1 for unidirec-
tional paths. For bi-directional operation, using half duplex for
multiple sources, it is possible to increase the signal reduction
O 100nA in standby mode
5mA typical operating conditions
O Cable reduction: 25:4 or greater
to close to 10:1. Through the use of differential signaling, shield-
ing and EMI filters can also be minimized, further reducing the
cost of serialization. The differential signaling is also important
O Bi-directional operation 50:7 reduction or greater
O Differential signaling:
for providing a noise-insensitive signal that can withstand radio
90dBm EMI when using CTL in lab conditions using a near
and electrical noise sources. Major reduction in power con-
field probe
sumption allows minimal impact on battery life in ultra-portable
• Minimized shielding
applications. A unique word boundary technique assures that
• Minimized EMI filter
the actual word boundary is identified when the data is deserial-
• Minimum susceptibility to external interference
ized. This guarantees that each word is correctly aligned at the
deserializer on a word by word basis through a unique
O Up to 22 bits in either direction
sequence of clock and data that is not repeated except at the O Up to 20MHz parallel interface operation
Oword boundary. It is possible to use a single
cations including bi-directional operation.
PLL
for
most
awpwpw.lDi-ataSheet4U.Vcoomltage
translation
from
1.65V
to
3.6V
O Ultra-small and cost-effective packaging
O High ESD protection: !8kV HBM
O Parallel I/O power supply (VDDP) range between
1.65V to 3.6V
Applications
O Micro-controller or Pixel interfaces
O Image sensors
O Small displays
LCD, cell phone, digital camera, portable gaming, printer,
PDA, video camera, automotive
Ordering Code:
Order
Number
FIN24ACGFX
FIN24ACMLX
Package
Number
BGA042A
MLP040A
Package Description
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
Pb-Free package per JEDEC J-STD-020B.
BGA and MLP packages available in Tape and Reel only.
PSerDes¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500910
www.fairchildsemi.com

1 page




FIN24AC pdf
is present in the serial bit stream. The operation of the serializer
will otherwise remain the same.
The exact frequency that the reference clock needs to run at will
be dependent upon the stability of the CKREF and STROBE
signal. If the source of the CKREF signal implements spread
spectrum technology then the maximum frequency of this
spread spectrum clock should be used in calculating the ratio of
STROBE frequency to the CKREF frequency. Similarly if the
STROBE signal has significant cycle-to-cycle variation then the
maximum cycle-to-cycle time needs to be factored into the
selection of the CKREF frequency.
Serializer Operation: (Figure 3)
DIRI equals 1
No CKREF
A third method of serialization can be done by providing a free
running bit clock on the CKSI signal. This mode is enabled by
grounding the CKREF signal and driving the DIRI signal HIGH.
At power-up the device is configured to accept a serialization
clock from CKSI. If a CKREF is received then this device will
enable the CKREF serialization mode. The device will remain in
this mode even if CKREF is stopped. To re-enable this mode
the device must be powered down and then powered back up
with a “logic 0” on CKREF.
FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE)
FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE)
FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
5 www.fairchildsemi.com

5 Page





FIN24AC arduino
Power Supply Currents
Symbol
IDDA1
IDDA2
IDDS1
IDDS2
IDD_PD
IDD_SER1
Parameter
VDDA Serializer Static
Supply Current
VDDA Deserializer Static
Supply Current
VDDS Serializer Static
Supply Current
VDDS Deserializer Static
Supply Current
VDD Power-Down Supply Current
IDD_PD = IDDA  IDDS  IDDP
26:1 Dynamic Serializer
Power Supply Current
IDD_SER1 = IDDA  IDDS  IDDP
IDD_DES1
1:26 Dynamic Deserializer
Power Supply Current
IDD_DES1 = IDDA  IDDS  IDDP
IDD_SER2
26:1 Dynamic Serializer Power
Supply Current
IDD_SER2 = IDDA  IDDS  IDDP
Test Conditions
All DP and Control Inputs at 0V or VDD
NOCKREF, S2 = 0, S1 = 1, DIR = 1
All DP and Control Inputs at 0V or VDD
NOCKREF, S2 = 0, S1 = 1, DIR = 0
All DP and Control Inputs at 0V or VDD
NOCKREF, S2 = 0, S1 = 1, DIR = 1
All DP and Control Inputs at 0V or VDD
NOCKREF, S2 = 0, S1 = 1, DIR = 0
S1 = S2 = 0,
All Inputs at GND or VDD
S2 = L
2 MHz
CKREF = STROBE
S1 = H 5 MHz
DIRI = H
S2 = H 5 MHz
See Figure 13
S1 = L 15 MHz
S2 = H 10 MHz
S1 = H 20 MHz
S2 = L 2 MHz
CKREF = STROBE
S1 = H 5 MHz
DIRI = L
S2 = H 5 MHz
See Figure 13
S1 = L 15 MHz
S2 = H 10 MHz
S1 = H 20 MHz
NO CKREF
2 MHz
STROBE o Active
5 MHz
CKSI = 15X Strobe
10 MHz
DIRI = H See Figure 13
15 MHz
Min
Typ
450
550
4.0
4.5
0.1
9.0
14.0
9.5
17.0
11.0
15.5
5.5
6.0
4.0
5.5
7.5
10.0
8.0
8.5
10.0
12.0
Max
Units
PA
PA
mA
mA
PA
mA
mA
mA
11 www.fairchildsemi.com

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