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PDF FIN24C Data sheet ( Hoja de datos )

Número de pieza FIN24C
Descripción uSerDes Low Voltage 24-Bit Bi-Directional Serializer/Deserializer
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FIN24C Hoja de datos, Descripción, Manual

April 2005
Revised September 2005
FIN24C
PSerDes¥
Low Voltage 24-Bit Bi-Directional Serializer/Deserializer
General Description
Features
The FIN24C PSerDes¥ is a low power Serializer/Deserializer O Low power for minimum impact on battery life
(SerDes) that can help minimize the cost and power of transfer-
• Multiple power-down modes
ring wide signal paths. Through the use of serialization, the
• AC coupling with DC balance
number of signals transferred from one point to another can be
significantly reduced. Typical reduction is 4:1 to 6:1 for unidirec-
tional paths. For bi-directional operation, using half duplex for
multiple sources, it is possible to increase the signal reduction
O 100nA in standby mode
5mA typical operating conditions
O Cable reduction: 25:4 or greater
to close to 10:1. Through the use of differential signaling, shield-
ing and EMI filters can also be minimized, further reducing the
cost of serialization. The differential signaling is also important
O Bi-directional operation 50:7 reduction or greater
O Up to 24 bits in either direction
for providing a noise-insensitive signal that can withstand radio
and electrical noise sources. Major reduction in power con-
sumption allows minimal impact on battery life in ultra-portable
O Up to 20MHz parallel interface operation
O Voltage translation from 1.8V to 3.3V
applications. A unique word boundary technique assures that
the actual word boundary is identified when the data is deserial-
ized. This guarantees that each word is correctly aligned at the
O Ultra-small and cost-effective packaging
O High ESD protection: !8kV HBM
deserializer on a word by word basis through a unique
sequence of clock and data that is not repeated except at the Applications
Oword boundary. It is possible to use a single PLL for most awpwpw.lDi-ataSheet4U.com
cations including bi-directional operation.
Micro-controller or Pixel interfaces
O Image sensors
O Small displays
LCD, cell phone, digital camera, portable gaming, printer,
PDA, video camera, automotive
Ordering Code:
Order
Number
FIN24CGFX
(Preliminary)
FIN24CMLX
Package
Number
BGA042A
Package Description
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
MLP040A Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
Pb-Free package per JEDEC J-STD-020B.
BGA and MLP packages available in Tape and Reel only.
PSerDes¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500909
www.fairchildsemi.com

1 page




FIN24C pdf
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the device.
When both of the mode signals are driven to a LOW state the
PLL and references will be disabled, differential input buffers will
be shut off, differential output buffers will be placed into a HIGH
Impedance state, LVCMOS outputs will be placed into a HIGH
Impedance state and LVCMOS inputs will be driven to a valid
level internally. Additionally all internal circuitry will be reset. The
loss of CKREF state is also enabled to insure that the PLL will
only power-up if there is a valid CKREF signal.
In a typical application the device will only change between the
power-down mode and the selected mode of operation. This
allows for system level power-down functionality to be imple-
mented via a single wire for a SerDes pair. The S1 and S2
selection signals that have their operating mode driven to a
“logic 0” should be hardwired to GND. The S1 and S2 signals
that have their operating mode driven to a “logic 1” should be
connected to a system level power-down signal.
Serializer Operation
The serializer configuration is described in the following sec-
tions. The basic serialization circuitry works essentially identi-
cally in these modes, but the actual data and clock streams will
differ depending on if CKREF is the same as the STROBE sig-
nal or not. When it is stated that CKREF equals STROBE this
means that the CKREF and STROBE signals are hardwired
together as one signal. When it is stated that CKREF does not
equal STROBE then each signal is distinct and CKREF must be
running at a frequency high enough to avoid any loss of data
condition. CKREF must never be a lower frequency than
STROBE.
Serializer Operation: (Figure 1)
DIRI equals 1
CKREF equals STROBE
The PLL must receive a stable CKREF signal in order to
achieve lock prior to any valid data being sent. The CKREF sig-
nal can be used as the data STROBE signal provided that data
can be ignored during the PLL lock phase.
Once the PLL is stable and locked the device can begin to cap-
ture and serialize data. Data will be captured on the rising edge
of the STROBE signal and then serialized. The serialized data
stream is synchronized and sent source synchronously with a
bit clock with an embedded word boundary. Serialized data is
sent at 26 times the CKREF clock rate. Two additional data bits
are sent that define the word boundary. When operating in this
mode the internal deserializer circuitry is disabled including the
serial clock, serial data input buffers, the bidirectional parallel
outputs and the CKP word clock. The CKP word clock will be
driven HIGH.
Serializer Operation: (Figure 2)
DIRI equals 1
CKREF does not equal STROBE
If the same signal is not used for CKREF and STROBE, then
the CKREF signal must be run at a higher frequency than the
STROBE rate in order to serialize the data correctly. The actual
serial transfer rate will remain at 26 times the CKREF fre-
quency. A data bit value of zero will be sent when no valid data
is present in the serial bit stream. The operation of the serializer
will otherwise remain the same.
The exact frequency that the reference clock needs to run at will
be dependent upon the stability of the CKREF and STROBE
signal. If the source of the CKREF signal implements spread
spectrum technology then the maximum frequency of this
spread spectrum clock should be used in calculating the ratio of
STROBE frequency to the CKREF frequency. Similarly if the
STROBE signal has significant cycle-to-cycle variation then the
maximum cycle-to-cycle time needs to be factored into the
selection of the CKREF frequency.
Serializer Operation: (Figure 3)
DIRI equals 1
No CKREF
A third method of serialization can be done by providing a free
running bit clock on the CKSI signal. This mode is enabled by
grounding the CKREF signal and driving the DIRI signal HIGH.
At power-up the device is configured to accept a serialization
clock from CKSI. If a CKREF is received then the device will
enable the CKREF serialization mode. The device will remain in
this mode even if CKREF is stopped. To re-enable this mode
the device must be powered down and then powered back up
with “logic 0” on CKREF.
5 www.fairchildsemi.com

5 Page





FIN24C arduino
Absolute Maximum Ratings(Note 2)
Recommended Operating Conditions
Supply Voltage (VDDP)
ALL Input/Output Voltage
LVDS Output Short Circuit Duration
Storage Temperature Range (TSTG)
Maximum Junction Temperature (TJ)
Lead Temperature (TL)
(Soldering, 4 seconds)
ESD Rating
Human Body Model, 1.5K:, 100pF
All Pins
CKSO, CKSI, DSO to GND
Machine Model, 0:, 200pF
0.5V to 4.6V
0.5V to 4.6V
Continuous
65qC to 150qC
150qC
260qC
!2kV
!8kV
!200V
Supply Voltage (VDDA, VDDS)
Supply Voltage (VDDP)
Operating Temperature (TA) (Note 2)
Supply Noise Voltage (VDDA-PP)
2.5V to 2.9V
1.65V to 3.6V
30qC to  70qC
100 mVP-P
Note 2: Absolute maximum ratings are DC values beyond which the device may be
damaged or have its useful life impaired. The datasheet specifications should be met,
without exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recommend oper-
ation outside datasheet specifications.
DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
LVCMOS I/O
VIH
VIL
VOH
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
VOL Output Low Voltage
IIN Input Current
DIFFERENTIAL I/O
IODH
IODL
IOZ
IIZ
VICM
VGO
Output HIGH Source Current
Output LOW Sink Current
Disabled Output Leakage Current
Disabled Input Leakage Current
Input Common Mode Range
Input Voltage Ground Off-set
Relative to Driver (Note 4)
RTRM
CKSI Internal Receiver
Termination Resistor
RTRM
DSI Internal Receiver
Termination Resistor
Test Conditions
Min Typ Max
Unit
(Note 3)
IOH = 2.0 mA
IOL = 2.0 mA
VIN = 0V to 3.6V
0.65 x VDDP
GND
VDDP = 3.3 r 0.3
VDDP = 2.5 r 0.2
VDDP = 1.8 r 0.15
VDDP = 3.3 r 0.3
VDDP = 2.5 r 0.2
VDDP = 1.8 r 0.15
0.75 x VDDP
5.0
VDDP
0.35 x VDDP
V
V
0.25 x VDDP V
5.0 PA
VOS = 1.0V, Figure 11
VOS = 1.0V, Figure 11
CKSO, DSO = 0V to VDDS, S2 = S1 = 0V
CKSI, DSI = 0V to VDDS, S2 = S1 = 0V
VDDS = 2.775 r 5%
see Figure 12
VID = 50mV, VIC = 925mV, DIRI = 0
| CKSI - CKSI | = VID
VID = 50mV, VIC = 925mV, DIRI = 0
| DSI - DSI | = VID
1.75
0.95
r0.1
r0.1
VGO  0.80
0
r5.0
r5.0
80.0 100 120
80.0 100 120
mA
mA
PA
PA
V
V
:
:
Note 3: Typical Values are given for VDD = 2.775V and TA = 25qC. Positive current values refer to the current flowing into device and negative values means current flowing out
of pins. Voltage are referenced to GROUND unless otherwise specified (except 'VOD and VOD).
Note 4: VGO is the difference in device ground levels between the CTL Driver and the CTL Receiver.
11 www.fairchildsemi.com

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