|
|
PDF FIN212AC Data sheet ( Hoja de datos )
| Número de pieza | FIN212AC | |
| Descripción | 12-Bit Serializer Deserializer | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de FIN212AC (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
March 2007
FIN212AC
12-Bit Serializer Deserializer with Multiple Frequency Ranges
Features
Description
Low Power Consumption
Low Power, Proprietary, CTL I/O Serial Interface
The FIN212AC µSerDes is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 12-bit data path to
Wide PLL Input Frequency Range
Wide Parallel Supply Voltage Range: 1.65 to 3.6V
four wires. The device can be configured as a serializer
or deserializer through the DIRI pin, minimizing
component types in the system. For camera
Low Power Core Operation: VDDS/A=2.5 to 3.6V
Built-in LV-CMOS Voltage Translation Capability
with no External Components
Adjustable Parallel Edge Rate
applications, an additional master clock can be passed
in the opposite direction of data flow.
The device utilizes Fairchild’s proprietary ultra-low
power, low-EMI technology. LV-CMOS parallel output
buffers have been implemented with slew rate control to
Operates as Serializer or Deserializer
Standby Power-Down Mode Support
adjust for capacitive loading and to minimize EMI. The
device also supports an ultra-low power-down mode for
conserving power in battery-operated applications
Built-in Differential Termination
Thewww.DataSheet4U.com device is available in a 5x5mm MLP package to
attach directly to a flex circuit, or in two choices of BGA,
Applications
where space constraints are a concern.
8-Bit LCD Displays for Cell Phones
8/10-Bit Cell Phone Camera Interface
8-Bit LCD Displays for Printers
Related Application Notes
AN-5058 µSerDes™ Family Frequently Asked
Questions
AN-5061 µSerDes™ Layout Guidelines
Ordering Information
Order Number
Package
Pb-
Free
FIN212ACMLX MLP032A Yes
FIN212ACGFX BGA42A
Yes
FIN212ACBFX
BGA36A
(Preliminary)
Yes
Operating
Temperature
Range
-30 to 70°C
-30 to 70°C
-30 to 70°C
Package Description
32-Terminal Molded Leadless Package
(MLP), Quad, JEDEC MO-220, 5mm square
42-Ball Ultra Small-Scale Ball Grid Array
(USS-BGA), JEDEC MO-195, 3.5 x 4.5mm
wide, 0.5mm Ball Pitch
36-Ball Ultra Small Scale Ball Grid Array
(USS-BGA), JEDEC MO-xxx 2.5mm square,
0.4mm Ball Pitch
Packing
Method
Tape &
Reel
Tape &
Reel
Tape &
Reel
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
1 page  
Power-Down Functionality: When both S1 and S0
signals are 0, regardless of the state of the DIRI
signal, the FIN212AC resets and powers down. The
power-down mode shuts down all internal analog
circuitry, disables the serial input and output of the
device, and resets all internal digital logic. Table 5
indicates the state of the output buffers in Power-
Down mode.
Signal Pins
DIRI=1
DIRI=0
DP[10:1]
Inputs Disabled
DP[12:11] Inputs Disabled
CKP
HIGH
STROBE
Input Disabled
CKREF
Input Disabled
/DIRO
0
Table 5. Output States
Outputs HIGH-Z
Outputs HIGH-Z
Outputs HIGH-Z
Input Disabled
Input Disabled
1
When an input is disabled, it does not draw current,
regardless of the state or level of the input signal.
All of the LV-CMOS inputs must remain driven during
power-down to ensure a low-power state
Turn-Around Functionality: The device passes and
inverts the DIRI signal asynchronously to the /DIRO
signal. Care must be taken by the system designer to
ensure that no contention occurs between the
deserializer outputs and the other devices on this port.
Optimally the peripheral device driving the serializer
should be put into a HIGH-impedance state prior to the
DIRI signal being asserted. When a device with
dedicated data outputs turns from a deserializer to a
serializer, the dedicated outputs remain at the last
logical value asserted. This value only changes if the
device is once again turned around into a deserializer
and the values are overwritten.
Strobe Pass-Through Mode: For some applications,
it is desirable to pass a word clock across a
differential signal pair in the opposite direction of
serialization. The FIN212 supports this mode of
operation. The following describes how to enable this
functionality.
Deserializer Configuration (DIRI=0)
1. CKREF LOW
2. Master clock connected DES to STROBE
Serializer Configuration (DIRI=1)
1. CKSI passes signal to serializer CKP
[CTL_ADJ] CTL Drive Adjustment: The drive
characteristics of the CTL I/O can be adjusted through
the CTL_ADJ pin. Standard-level CTL drive is
provided when the CTL_ADJ pin is zero. High- level
drive is provided when CTL_ADJ pin is HIGH. High-
drive should be used in noisy environments or when
driving cables longer than 20cm. When in high-drive
mode, CTL drive increases by approximately by 50%.
CTL_ADJ
0
Description
Standard CTL Drive
1 High CTL Drive
Table 6. CTL_ADJ Functionality
[(/XTRM]] Test / XTRM Mode Functionality: For the
deserializer, the (XTRM) signal can be used to enable
or disable the internal termination resistor on the CKS
and DS signals of the deserializer. When the internal
termination is disabled, an external termination resistor
is required for the CTL I/O to operate properly.
(XTRM)
0
1
DIRI=0 (/XTRM)
Internal Termination
External Termination
Table 7. (/XTRM) Functionality
Serializer Configuration (DIRI=1)
1. Master CLK transmitted out of SER CKP
2. Drive the pixel_CLK [(/XTRM)] into SER TROBE
Deserializer Configuration (DIRI=0)
1. Pixel_CLK transmitted out of DES CKP
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
5
www.fairchildsemi.com
5 Page 
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDD
TSTG
TJ
TL
ESD
Parameter
Supply Voltage
All Input/Output Voltage
CTL Output Short-Circuit Duration
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature (Soldering, four seconds)
Human Body Model, 1.5KΩ, 100pF
Human Body Model, 1.5KΩ, Serial I/O Pins
Machine Model, 0Ω, 200pF
Min.
-0.5V
-0.5
Continuous
-65
+150
+260
Max.
+4.6
VDD+0.5
+150
8
14
400
Unit
V
V
°C
°C
°C
kV
kV
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDDA, VDDS
VDDP
TA
VDDA-PP
Parameter
Supply Voltage
Supply Voltage
Operating Temperature
Supply Noise Voltage
Min.
2.5
1.65
-30
100
Max.
3.6
3.6
+70
Unit
V
V
ºC
mVp-p
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet FIN212AC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| FIN212AC | 12-Bit Serializer Deserializer | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |