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PDF FDD6N50 Data sheet ( Hoja de datos )
| Número de pieza | FDD6N50 | |
| Descripción | N-Channel MOSFET | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FDD6N50 / FDU6N50
N-Channel UniFETTM MOSFET
500 V, 6 A, 900 mΩ
Features
• RDS(on) = 900 mΩ (Max.) @ VGS = 10 V, ID = 3 A
• Low Gate Charge (Typ. 12.8 nC)
• Low Crss (Typ. 9 pF)
• 100% Avalanche Tested
• Improved dv/dt Capability
Applications
• LCD/LED/PDP TV
• Lighting
• Uninterruptible Power Supply
• AC-DC Power Supply
D
November 2013
Description
UniFETTM MOSFET is Fairchild Semiconductor’s high voltage
MOSFET family based on planar stripe and DMOS technology.
This MOSFET is tailored to reduce on-state resistance, and to
provide better switching performance and higher avalanche
energy strength. This device family is suitable for switching
power converter applications such as power factor correction
(PFC), flat panel display (FPD) TV power, ATX and electronic
lamp ballasts.
D
G
S
D-PAK
GDS
I-PAK
Absolute Maximum Ratings TC = 25oC unless otherwise noted.
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
(Note 1)
Gate-Source voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation
(TC = 25°C)
- Derate Above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8” from Case for
5 Seconds
G
S
FDD6N50TM /
FDD6N50TM_WS /
FDU6N50TU
500
6
3.8
24
±30
270
6
8.9
4.5
89
0.71
-55 to +150
300
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Thermal Characteristics
Symbol
RθJC
RθJA
Parameter
Thermal Resistance, Junction-to-Case, Max.
Thermal Resistance, Junction-to-Ambient, Max.
©2006 Fairchild Semiconductor Corporation
FDD6N50 / FDU6N50 Rev. C1
1
FDD6N50TM /
FDD6N50TM_WS /
FDU6N50TU
1.4
83
Unit
°C/W
www.fairchildsemi.com
1 page  
Same Type
50KΩ as DUT
12V 200nF
300nF
VGS
10V
Qg
VGS
VDS
Qgs Qgd
IG = co3nmsAt.
DUT
Charge
Figure 12. Gate Charge Test Circuit & Waveform
V10GVS
VDS
VGS
RG
RL
VDD
VDS
90%
DUT
VGS 10%
td(on)
tr
t on
Figure 13. Resistive Switching Test Circuit & Waveforms
td(off)
tf
t off
V1G0GVSS
tp
VDS
ID
RG
L
EAS = --21-- L IAS2
------B--V--D--S-S-------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
DUT
VDD
VDS (t)
t p Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2006 Fairchild Semiconductor Corporation
FDD6N50 / FDU6N50 Rev. C1
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet FDD6N50.PDF ] | |
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