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Número de pieza | STD03N | |
Descripción | (STD03N/P) Darlington Transistors | |
Fabricantes | Allegro MicroSystems | |
Logotipo | ||
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No Preview Available ! STD03N and STD03P
Darlington Transistors for Audio Amplifiers
Features and Benefits
▪ Built-in temperature compensation diodes
▪ High power (160 W) handling in a small package
(TO-3P), for minimized heat sink requirements
▪ Built-in drivers and temperature compensation diodes,
reducing external component count and simplifying
circuit design
▪ NPN and PNP versions
▪ Emitter terminals placed symmetrically, pin 5 on NPN
and pin 1 on PNP models, allowing adjacent placement on
PCB to minimize trace length and output skew when used
in pairs
▪ Approved by major manufacturers
Description
The STD03N and STD03Pare enhanced Darlington transistors
with built-in drivers and temperature compensation diode.
Manufactured using the unique Sanken thin-wafer production
technology, these devices achieve higher power levels through
decreased thermal resistance, and can withstand higher voltages
than similar devices on the market.
The temperature compensation diode is integrated on the same
chip as the power transistors. By this design, the STD03N and
STD03P eliminate delays that would otherwise be induced
between thermal sensing at the heat source, and the operation of
the compensation circuitry. Thus, these transistors are ideal for
applications where enhanced thermal stability is required.
Package: 5 pin TO-3P (MT-100)
This device is provided in a 5-pin TO-3P plastic package with
pin 4 removed. Contact Allegro® for application support and
additional information on device performance.
Applications include:
▪ General amplifier applications
▪ Public address amplifiers
▪ Carwww.DataSheet4U.com audio amplifiers
STD03N
STD03P
Not to scale
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Emitter pins symmetrical
Equivalent Circuits
STD03N
3
1
4
STD03P
1
25
5
3
Datasheet 28104.00a
1 page STD03N and
STD03P
STD03N
Terminal
Configuration
Darlington Transistors for Audio Amplifiers
PACKAGE OUTLINE DRAWING, TO-3P
STD03P
Terminal
Configuration
15.6 ±0.3
Gate Burr
4.8 ±0.2
2
+0.2
–0.1
Branding
XXXXXXXX
XXXXXXXX
1.74
+0.2
–0.1
1.34
+0.2
–0.1
1.05
+0.2
–0.1
1.7 ±0.1
Terminal dimension
at case surface
15.8 ±0.2
4×P2.54 ±0.1 = (10.16)
Terminal dimensions at case surface
4×P2.54 ±0.6 = 10.16 ±0.8
Terminal dimension at lead tips
0.65
+0.2
–0.1
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Gate burr: 0.3 mm (max.), mold flash may appear at opposite side
Terminal core material: Cu
Terminal treatment: Ni plating and solder dip
Heat sink material: Cu
Heat sink treatment: Ni plating
Leadform: 2804
Weight (approximate): 6.0 g
Dimensions in millimeters
Branding codes (exact appearance at manufacturer discretion):
1st line, type: STD03X
Where: X is the transistor type (N or P)
2nd line, lot: YMDD H
Where: Y is the last digit of the year of manufacture
M is the month (1 to 9, O, N, D)
DD is the 2-digit date
H is the hFE rating (O or Y; for values see
footnote, Electrical Characteristics table)
Leadframe plating Pb-free. Device composition
includes high-temperature solder (Pb >85%),
which is exempted from the RoHS directive.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet STD03N.PDF ] |
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