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PDF T6818 Data sheet ( Hoja de datos )
| Número de pieza | T6818 | |
| Descripción | (T6818 / T6828) Triple Halfbridge DMOS OUTPUT DRIVER | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Supply Voltage up to 40 V
• RDSon Typically 0.5 Ω at 25°C, Maximum 1.1 Ω at 150°C
• Up to 1.5 A Output Current
• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
• Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
• No Shoot-through Current
• Very Low Quiescent Current IS < 5 µA in Standby Mode versus Total Temperature
Range
• Outputs Short-circuit Protected
• Overtemperature Protection for Each Switch and Overtemperature Prewarning
• Undervoltage Protection
• Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• SO14 Power Package
Description
The T6818/T6828 are fully protected driver interfaces designed in 0.8-µm BCDMOS
technology. They are used to control up to 3 different loads by a microcontroller in
automotive and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A.
The drivers are internally connected to form 3 half-bridges and can be controlled sep-
arately from a standard serial data interface. Therefore, all kinds of loads such as
bulbs, resistors, capacitors and inductors can be combined. The IC design especially
supports the application of H-bridges to drive DC motors.www.DataSheet4U.com
Protection is guaranteed regarding short-circuit conditions, overtemperature and und-
er voltage. Various diagnostic functions and a ver y low quiescent current in
stand-by-mode opens a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
Triple Half-
bridge DMOS
Output Driver
with Serial Input
Control
T6818/T6828
Rev. 4530E–BCD–07/04
1 page  
T6818/T6828
Table 2. Output Data Protocol
Output (Status)
Bit
Register
Function
0 TP Temperature prewarning: high = warning
1 Status LS1 High = output is on, low = output is off; not affected by SRR
2 Status HS1 High = output is on, low = output is off; not affected by SRR
3 Status LS2 Description see LS1
4 Status HS2 Description see HS1
5 Status LS3 Description see LS1
6 Status HS3 Description see HS1
7 n. u. Not used
8 n. u. Not used
9 n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
Short circuit detected: set high when at least one high-side or
13
SCD
low-side switch is switched off by a short-circuit condition. Bits 1 to
6 can be used to detect the shorted switch.
Open load detected: set high, when at least one active high-side or
14
OPL
low-side switch sinks/sources a current below the open load
threshold current.
15 PSF Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
(OCS)
Bit 8
Bit 7
xx H x x x x x x
Bit 6
(HS3)
L
Bit 5
(LS3)
L
Bit 4
(HS2)
L
Bit 3
(LS2)
L
Bit 2
(HS1)
L
Bit 1
(LS1)
L
Bit 0
(SRR)
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
(OCS)
Bit 8
Bit 7
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3 Bit 2 Bit 1 Bit 0
(LS2) (HS1) (LS1) (SRR)
HH H H H L L L L L L L L LL L
HH H L L H H L L L L L L LL L
HH H L L L L H H L L L L LL L
4530E–BCD–07/04
5
5 Page 
T6818/T6828
Serial Interface – Timing
No. Parameters
Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max.
8.1
DO enable after CS
falling edge
CDO = 100 pF
9
1
tENDO
200
8.2
DO disable after CS
rising edge
CDO = 100 pF
9
2
tDISDO
200
8.3 DO fall time
CDO = 100 pF
9
-
tDOf
100
8.4 DO rise time
CDO = 100 pF
9
-
tDOr
100
8.5 DO valid time
CDO = 100 pF
9
10
tDOVal
200
8.6 CS setup time
4
4
tCSSethl
225
8.7 CS setup time
4
8
tCSSetlh
225
8.8 CS high time
49
tCSh 500
8.9 CLK high time
65
tCLKh
225
8.10 CLK low time
66
tCLKl
225
8.11 CLK period time
6-
tCLKp
500
8.12 CLK setup time
6
7
tCLKSethl
225
8.13 CLK setup time
6
3
tCLKSetlh
225
8.14 DI setup time
5 11
tDIset
40
8.15 DI hold time
5
12
tDIHold
40
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. See Figure 4 on page 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Type*
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
4530E–BCD–07/04
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet T6818.PDF ] | |
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