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PDF SY100S834L Data sheet ( Hoja de datos )
| Número de pieza | SY100S834L | |
| Descripción | Pecl Clock Generation | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)
CLOCK GENERATION CHIP
ClockWorks™
SY100S834
SY100S834L
FINAL
FEATURES
DESCRIPTION
s 3.3V and 5V power supply options
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,
s 50ps output-to-output skew
s Synchronous enable/disable
s Master Reset for synchronization
÷4, ÷8) clock generation chip designed explicitly for low
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
s Internal 75KΩ input pull-down resistors
be driven by either a differential or single-ended ECL or,
s Available in 16-pin SOIC package
if positive power supplies are used, PECL input signal.
In addition, by using the VBB output, a sinusoidal source
can be AC-coupled into the device. If a single-ended
input is to be used, the VBB output should be connected
PIN CONFIGURATION/BLOCK DIAGRAM
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
Q0 1
Q0 2
Q
÷1 or ÷2
R
QD
16 VCC
15 EN
can only source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input
is LOW, SY100S834/L functions as a divide by 2, by 4
VCC 3
R 14 FSEL
and by 8 clock generation chip. However, if FSEL input
is HIGH, it functions as a divide by 1, by 2 and by 4
Q1 4
Q1 5
Q
÷2 or ÷4
R
13 CLK
12 CLK
clock generation chip. This latter feature will increase
the clock frequency by two folds.
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The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
VCC 6
11 VBB
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
Q2 7
Q2 8
Q
÷4 or ÷8
R
10 MR
9 VEE
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
SOIC
TOP VIEW
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
PIN NAMES
multiple SY100S834/Ls in a system.
Pin
CLK
FSEL
EN
MR
VBB
Q0
Function
Differential Clock Inputs
Function Select
Synchronous Enable
Master Reset
Reference Output
Differential ÷1 or ÷2 Outputs
TRUTH TABLE
CLK
EN
ZL
ZZ H
XX
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
MR Function
L Divide
L Hold Q0–2
H Reset Q0–2
Q1 Differential ÷2 or ÷4 Outputs
FSEL
Q0 Outputs
Q1 Outputs
Q2 Outputs
Q2 Differential ÷4 or ÷8 Outputs
L
Divide by 2
Divide by 4
Divide by 8
H
Divide by 1
Divide by 2
Divide by 4
Rev.: F Amendment: /0
1 Issue Date: September, 1999
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100S834L.PDF ] | |
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