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Número de pieza | NLSF1174 | |
Descripción | Hex D Flip-Flop | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NLSF1174
Hex D Flip−Flop with
Common Clock and Reset
This device consists of six D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active low. All
inputs/outputs are standard CMOS compatible.
Features
• Output Drive Compatibility: 10 LSTTL Loads
• Outputs Directly Interface to CMOS
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• MSL Level 1
• Chip Complexity: 162 FET
• Pb−Free Package is Available*
Q0 Reset VCC
16 15
14
Q5
13
http://onsemi.com
QFN−16
MN SUFFIX
1 CASE 485G
MARKING DIAGRAM
16
1
ÇÇÇÇÇÇNLSF
1174
ALYW G
G
D0 1
D1 2
Q1 3
D2 4
12 D5www.DataSheet4U.com
11 D4
10 Q4
9 D3
56 7 8
Q2 GND Clock Q3
Center pad on bottom may be connected to VCC of device.
This pad must be isolated or connected to VCC.
Figure 1. PIN ASSIGNMENT (Top View)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 5
1
NLSF1174 = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Reset
L
H
H
H
H
FUNCTION TABLE
Inputs
Clock
D
XX
H
L
LX
X
Output
Q
L
H
L
No Change
No Change
ORDERING INFORMATION
Device
Package
Shipping†
NLSF1174MNR2 QFN−16 3000 / Tape & Reel
NLSF1174MNR2G QFN−16 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NLSF1174/D
1 page NLSF1174
CLOCK
tr
90%
50%
10%
tw
1/fmax
tf
tPLH
tPHL
90%
Q 50%
10%
tTLH
tTHL
VCC
GND
Figure 4. Switching Waveform
RESET
tPHL
Q
tw
50%
CLOCK
trec
50%
Figure 5. Switching Waveform
VCC
GND
VCC
GND
DATA
CLOCK
VALID
50%
tsu
th
50%
VCC
GND
VCC
GND
Figure 6. Switching Waveform
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
PIN1/PRODUCT ORIENTATION CARRIER TAPE
USER DIRECTION OF FEED
Figure 8.
http://onsemi.com
5
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet NLSF1174.PDF ] |
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