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PDF NIF9N05CL Data sheet ( Hoja de datos )
| Número de pieza | NIF9N05CL | |
| Descripción | Protected Power MOSFET | |
| Fabricantes | ON Semiconductor | |
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NIF9N05CL
Protected Power MOSFET
2.6 A, 52 V, N−Channel, Logic Level,
Clamped MOSFET w/ ESD Protection
in a SOT−223 Package
Benefits
• High Energy Capability for Inductive Loads
• Low Switching Noise Generation
Features
• Diode Clamp Between Gate and Source
• ESD Protection − HBM 5000 V
• Active Over−Voltage Gate to Drain Clamp
• Scalable to Lower or Higher RDS(on)
• Internal Series Gate Resistance
• Pb−Free Packages are Available
Applications
• Automotive and Industrial Markets:
Solenoid Drivers, Lamp Drivers, Small Motor Drivers
www.DataSheet4U.com
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage Internally Clamped VDSS
52−59
V
Gate−to−Source Voltage − Continuous
VGS ±15 V
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp = 10 ms) (Note 1)
ID
2.6 A
IDM 10
Total Power Dissipation @ TA = 25°C (Note 1) PD
1.69 W
Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C
Single Pulse Drain−to−Source
Avalanche Energy (VDD = 50 V, ID(pk) = 1.17
A, VGS = 10 V, L = 160 mH, RG = 25 W)
EAS
110 mJ
Thermal Resistance,
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
RqJA
RqJA
°C/W
74
169
Maximum Lead Temperature for Soldering TL 260 °C
Purposes, 1/8″ from Case for 10 Seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to a FR4 board using 1″ pad size, (Cu area 1.127 in2).
2. When surface mounted to a FR4 board using minimum recommended pad
size, (Cu area 0.412 in2).
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 5
1
http://onsemi.com
VDSS
(Clamped)
52 V
RDS(ON) TYP
107 mW
ID MAX
2.6 A
Gate
(Pin 1)
Overvoltage
Protection
RG
ESD Protection
Drain
(Pins 2, 4)
MPWR
Source
(Pin 3)
SOT−223
CASE 318E
STYLE 3
MARKING DIAGRAM
GATE
DRAIN
SOURCE
1
2
3
4
DRAIN
(Top View)
A = Assembly Location
Y = Year
W = Work Week
F9N05 = Specific Device Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NIF9N05CL/D
1 page  
NIF9N05CL
TYPICAL PERFORMANCE CURVES
500
Ciss
400 VDS = 0 V VGS = 0 V
300 Crss
TJ = 25°C
5
VDS
4
QGS
3
QT
QGD
50
VGS
40
30
200 Ciss 2
20
100
0
10
5 05
VGS VDS
Coss
Crss
10 15 20 25 30 35
1
0
0
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
10
ID = 2.6 A
TJ = 25°C
0
1234 5
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source Voltage vs. Total
Gate Charge
100000
10000
VDD = 40 V
ID = 2.6 A
VGS = 10 V
1000
100
td(off)
tf
tr
td(on)
3
VGS = 0 V
TJ = 25°C
2
1
10
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistance Switching Time Variation
vs. Gate Resistance
0
0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage vs. Current
ORDERING INFORMATION
Device
Package
Shipping†
NIF9N05CLT1
NIF9N05CLT1G
SOT−223
SOT−223
(Pb−Free)
1000 / Tape & Reel
NIF9N05CLT3
SOT−223
NIF9N05CLT3G
SOT−223
(Pb−Free)
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NIF9N05CL.PDF ] | |
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