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PDF AT89LP216 Data sheet ( Hoja de datos )

Número de pieza AT89LP216
Descripción 8-bit Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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Features
8-bit Microcontroller Compatible with MCS®51 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 128 x 8 Internal RAM
– 4-level Interrupt Priority
Nonvolatile Program Memory
– 2K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: Minimum 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 64-byte User Signature Array
– 2-level Program Memory Lock for Software Security
Peripheral Features
– Two 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Programmable Watchdog Timer with Software Reset
– Analog Comparator with Selectable Interrupt and Debouncing
– 8 General-purpose Interrupt Pins
Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Internal 8 MHz RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
I/O and Packages
– Up to 14 Programmable I/O Lines
– Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
– 5V Tolerant I/O
– 16-lead TSSOP, SOIC or PDIP
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40C to 85°C Temperature Range
8-bit
Microcontroller
with 2K Bytes
Flash
AT89LP216
1. Description
The AT89LP216 is a low-power, high-performance CMOS 8-bit microcontroller with
2K bytes of In-System Programmable Flash memory. The device is manufactured
using Atmel®'s high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The AT89LP216 is built around an
enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-
tions to execute in 12, 24 or 48 clock cycles. In the AT89LP216 CPU, instructions
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AT89LP216 pdf
AT89LP216
5.3 Interrupt Handling
The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In
order for an interrupt to be serviced at the end of an instruction, its flag needs to have been
latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of
the previous instruction if the current instruction executes in only a single clock cycle.
The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once
every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response,
this leads to a higher maximum rate of incidence for the external interrupts.
5.4 Timer/Counters
By default the Timer/Counters is incremented at a rate of once per clock cycle. This compares to
once every 12 clocks in the standard 8051. A common prescaler is available to divide the time
base for all timers and reduce the increment rate. The TPS bits in the CLKREG SFR control the
prescaler (Table 9-2 on page 13). Setting TPS = 1011B will cause the timers to count once every
12 clocks.
The external Timer/Counter pins, T0 and T1, are sampled at every clock cycle instead of once
every 12 clock cycles. This increases the maximum rate at which the Counter modules may
function.
5.5 Serial Port
The baud rate of the UART in Mode 0 is 1/2 the clock frequency, compared to 1/12 the clock fre-
quency in the standard 8051; and output data is only stable around the rising edge of the serial
clock. In should also be noted that when using Timer 1 to generate the baud rate in Mode 1 or
Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain
the same baud rate in the AT89LP216 while running at the same frequency as a standard 8051,
the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to
facilitate longer time-out periods for generating low baud rates.
5.6 Watchdog Timer
The Watchdog Timer in AT89LP216 counts at a rate of once per clock cycle. This compares to
once every 12 clocks in the standard 8051. A common prescaler is available to divide the time
base for all timers and reduce the counting rate.
5.7 I/O Ports
The I/O ports of the AT89LP216 may be configured in four different modes. By default all the I/O
ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports
are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be
put into quasi-bidirectional mode by clearing the P1M0 and P3M0 SFRs. The user can also con-
figure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port User Fuse.
When this fuse is disabled, P1M0 and P3M0 will reset to 00h instead of FFh and the ports will be
weakly pulled high.
5.8 Reset
The RST pin of the AT89LP216 is active-low as compared with the active high reset in the stan-
dard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a
minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset.
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AT89LP216 arduino
AT89LP216
9. System Clock
The system clock is generated directly from one of three selectable clock sources. The three
sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The
clock source is selected by the Clock Source User Fuses as shown in Table 9-1. No internal
clock division is used to generate the CPU clock from the system clock. See “User Configuration
Fuses” on page 71.
Table 9-1. Clock Source Settings
Clock Source
Fuse 1
Clock Source
Fuse 0
Selected Clock Source
0 0 Crystal Oscillator
0 1 Reserved
1 0 External Clock on XTAL1
1 1 Internal 8 MHz RC Oscillator
9.1 Crystal Oscillator
When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and
XTAL2. Note that the internal structure of the device adds about 10 pF of capacitance to both
XTAL1 and XTAL2, so that in some cases an external capacitor may NOT be required. It is rec-
ommended that a resistor R1 be connected to XTAL1, instead of load capacitor C1, for improved
startup performance. The total capacitance on XTAL1 or XTAL2, including the external load
capacitor plus internal device load, board trace and crystal loadings, should not exceed 20 pF.
When using the crystal oscillator, P3.2 and P3.3 will have their inputs and outputs disabled.
When using the crystal oscillator, XTAL2 should not be used to drive a board-level clock without
a buffer
Figure 9-1. Crystal Oscillator Connections
C2
~10 pF
R1
~10 pF
Note: 1. C2
R1
= 0–10 pF for Crystals
= 0–10 pF for Ceramic Resonators
= 4–5 MΩ
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