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PDF NCP5424 Data sheet ( Hoja de datos )
| Número de pieza | NCP5424 | |
| Descripción | Dual Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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NCP5424
Dual Synchronous
Buck Controller with Input
Current Sharing
The NCP5424 is a flexible dual N−Channel synchronous buck
controller utilizing V2t control for fast transient response and
excellent line and load regulation. This highly versatile controller can
be configured as a single two phase output converter that draws
programmable amounts of current from two different input voltages or
all current from one supply. The NCP5424 can also be configured as
two independent out−of−phase controllers.
Using the NCP5424 in a current sharing input configuration is ideal
for applications where more power is required than is available from
one supply, such as video cards or other plug−in boards. When
configured as a dual output controller, the output of one controller can
be divided down and used as the reference for the second controller.
This tracking capability is useful in applications such as Double Data
Rate (DDR) Memory power where the termination voltage must track
VDD.
The NCP5424 provides a cycle−to−cycle current limit on
Controller 2 allowing the system to handle transient overcurrent
events and a hiccup mode overcurrent protection on Controller 1
allowing lossless short circuit protection. In addition, the NCP5424
provides Soft−Start, undervoltage lockout, and built−in adaptive FET
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nonoverlap time to prevent shoot through.
Features
• Hiccup Mode Current Limit (Controller 1)
• Cycle−to−Cycle Current Limit (Controller 2)
• Programmable Soft−Start
• 100% Duty Cycle for Enhanced Transient Response
• 150 kHz to 600 kHz Programmable Frequency Operation
• Switching Frequency Set by Single Resistor
• Out−Of−Phase Synchronization Between the Channels Reduces the
Input Filter Requirement
• Undervoltage Lockout
• Pb−Free Packages are Available*
Applications
• Video Graphics Card
• DDR Memory
• High Current (Two−Phase) Power Supplies
• Dual Output DC−DC Converters
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16
1
SOIC−16
D SUFFIX
CASE 751B
PIN CONNECTIONS AND
MARKING DIAGRAM
1
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS−
VFB1
COMP1
16
GATE(H)2
GATE(L)2
VCC
ROSC
IS+2
VFB+2
VFB−2
COMP2
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NCP5424D
SOIC−16
48 Units/Rail
NCP5424DG
NCP5424DR2
SOIC−16
(Pb−Free)
SOIC−16
48 Units/Rail
2500 Tape & Reel
NCP5424DR2G SOIC−16 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 4
1
Publication Order Number:
NCP5424/D
1 page  
NCP5424
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 mF,
10.8 V < VCC < 13.2 V; 10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, VFB+2 = 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
ROSC Voltage
Phase Difference
ROSC = 61.9 k; Measure GATE(H)1; Note 3
ROSC = 30.9 k; Measure GATE(H)1
ROSC = 15.1 k; Measure GATE(H)1; Note 3
ROSC = 30.9 k, Note 3
−
112
250
450
0.970
−
150
300
600
1.000
180
188
350
750
1.030
−
Supply Currents
VCC Current
BST Current
COMP1,2 = 0 V (No Switching)
COMP1,2 = 0 V (No Switching)
− 13 17
− 3.5 6.0
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1,2 charging
7.8 8.6 9.4
Stop Threshold
GATE(H) not switching; COMP1,2 discharging
7.0
7.8
8.6
Hysteresis
Start−Stop
0.5 0.8 1.5
Hiccup Mode Overcurrent Protection (Controller 1)
OVC Comparator Offset Voltage
0 V < IS+ 1 < 5.5 V, 0 V < IS− < 5.5 V
55 70 85
Discharge Threshold
− 0.20 0.25 0.30
IS+ 1 Bias Current
0 V < IS+ 1 < 5.5 V
−1.0
0.1
1.0
IS− Bias Current
0 V < IS− < 5.5 V
−2.0
0.2
2.0
OVC Common Mode Range
− 0 − 5.5
OVC Latch COMP1 Discharge Current COMP1 = 1.0 V
2.0 5.0 8.0
Cycle−to−Cycle Current Limit (Controller 2)
OVC Comparator Offset Voltage
0 V < IS+ 2 < 5.5 V, 0 V < IS− < 5.5 V
55 70 85
IS+ 2 Bias Current
0 V < IS+ 2 < 5.5 V
−1.0
0.1
1.0
OVC Common Mode Range
− 0 − 5.5
OVC Latch COMP2 Discharge Current COMP = 1.0 V
0.3 1.2 3.5
3. Guaranteed by design, not 100% tested in production.
Unit
kHz
kHz
kHz
V
°
mA
mA
V
V
V
mV
V
mA
mA
V
mA
mV
mA
V
mA
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5
5 Page 
NCP5424
commonly used. Powdered iron cores are very suitable due
to its high saturation flux density and have low loss at high
frequencies, a distributed gap and exhibit very low EMI.
The minimum value of inductance which prevents
inductor saturation or exceeding the rated FET current can
be calculated as follows:
LMIN
+
(VIN(MIN) * VOUT)VOUT
fSW VIN(MIN) ISW(MAX)
where:
LMIN = minimum inductance value;
VIN(MIN) = minimum design input voltage;
VOUT = output voltage;
fSW = switching frequency;
ISW(MAX) − maximum design switch current.
The inductor ripple current can then be determined:
DIL
+
VOUT
L
(1 * D)
fSW
where:
DIL = inductor ripple current;
VOUT = output voltage;
L = inductor value;
D = duty cycle.
fSW = switching frequency
The designer can now verify if the number of output
capacitors will provide an acceptable output voltage ripple
(1.0% of output voltage is common). The formula below is
used:
DIL
+
DVOUT
ESRMAX
Rearranging we have:
ESRMAX
+
DVOUT
DIL
where:
ESRMAX = maximum allowable ESR;
DVOUT = 1.0% × VOUT = maximum allowable output
voltage ripple ( budgeted by the designer );
DIL = inductor ripple current;
VOUT = output voltage.
The number of output capacitors is determined by:
Number
of
capacitors
+
ESRCAP
ESRMAX
where:
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet).
The designer must also verify that the inductor value
yields reasonable inductor peak and valley currents (the
inductor current is a triangular waveform):
IL(PEAK)
+
IOUT
)
DIL
2
where:
IL(PEAK) = inductor peak current;
IOUT = load current;
DIL = inductor ripple current.
IL(VALLEY)
+
IOUT
*
DIL
2
where:
IL(VALLEY) = inductor valley current.
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
ǒ ǓDVOUT + DIOUT
ESL
Dt
)
ESR
)
tTR
COUT
where:
DIOUT / Dt = load current slew rate;
DIOUT = load transient;
Dt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
tTR = output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula:
ESRMAX
+
DVESR
DIOUT
where:
DVESR = change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
Number
of
capacitors
+
ESRCAP
ESRMAX
where:
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet).
ESRMAX = maximum allowable ESR.
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11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NCP5424.PDF ] | |
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