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PDF NCP5423 Data sheet ( Hoja de datos )

Número de pieza NCP5423
Descripción (NCP5422A / NCP5423) Dual Out-of-Phase Synchronous Buck Controller
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No Preview Available ! NCP5423 Hoja de datos, Descripción, Manual

NCP5422A, NCP5423
Dual Out−of−Phase
Synchronous
Buck Controller
with Current Limit
The NCP5422A/3 is a dual N−channel synchronous buck regulator
controller. It contains all the circuitry required for two independent
buck regulators and utilizes the V2t control method to achieve the
fastest possible transient response and best overall regulation, while
using the least number of external components. The NCP5422A/3
features out−of−phase synchronization between the channels,
reducing the input filter requirement. The NCP5422A/3 also provides
undervoltage lockout, Soft−Start, built in adaptive non−overlap time
and hiccup mode overcurrent protection.
Features
V2 Control Topology
Hiccup Mode Overcurrent Protection
150 ns Transient Response
Programmable Soft−Start
100% Duty Cycle for Enhanced Transient Response
150 kHz to 600 kHz Programmable Frequency Operation
Switching Frequency Set by Single Resistor
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Out−Of−Phase Synchronization Between Channels
Undervoltage Lockout
Both Gate Drive Outputs Held Low During Fault Condition
Pb−Free Packages are Available
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16
1
SO−16
AD SUFFIX
CASE 751B
MARKING DIAGRAMS AND
PIN CONNECTIONS
1
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS−1
VFB1
COMP1
16
GATE(H)2
GATE(L)2
VCC
ROSC
IS+2
IS−2
VFB2
COMP2
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
NCP5422ADR2
SO−16 2500 Tape & Reel
NCP5422ADR2G SO−16 2500 Tape & Reel
(Pb−Free)
NCP5423DR2G
SO−16 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 7
1
Publication Order Number:
NCP5422A/D

1 page




NCP5423 pdf
NCP5422A, NCP5423
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 mF,
10.8 V < VCC < 13.2 V; 10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.)
Characteristic
Test Conditions
Min Typ
Supply Currents
VCC Current
BST Current
COMP1,2 = 0 V (No Switching)
COMP1,2 = 0 V (No Switching)
− 13
− 3.5
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1,2 charging
7.8 8.6
Stop Threshold
GATE(H) not switching; COMP1,2 discharging
7.0
7.8
Hysteresis
Start−Stop
0.5 0.8
Hiccup Mode Overcurrent Protection
OVC Comparator Offset Voltage
0 V < IS+ 1(2) < 5.5 V, 0 V < IS− 1(2) < 5.5 V
55
70
Discharge Threshold
− 0.20 0.25
IS+ 1(2) Bias Current
0 V < IS+ 1(2) < 5.5 V
−1.0 0.1
IS− 1(2) Bias Current
0 V < IS− 1(2) < 5.5 V
−1.0 0.1
OVC Common Mode Range
Note 3
0−
OVC Latch COMP1 Discharge Current COMP1 = 1.0 V
2.0 5.0
OVC Latch COMP2 Discharge Current COMP2 = 1.0 V
0.3 1.2
COMP1 Charge/Discharge Ratio in OVC
5.0 6.0
3. Guaranteed by design, not 100% tested in production.
Max
17
6.0
9.4
8.6
1.5
85
0.30
1.0
1.0
5.5
8.0
3.5
7.0
Unit
mA
mA
V
V
V
mV
V
mA
mA
V
mA
mA
PACKAGE PIN DESCRIPTION
PIN NO.
PIN SYMBOL
FUNCTION
1
GATE(H)1
High Side Switch FET driver pin for channel 1.
2
GATE(L)1
Low Side Synchronous FET driver pin for channel 1.
3
GND
Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC.
4 BST Power input for GATE(H)1 and GATE(H)2 pins.
5
IS+1
Positive input for channel 1 overcurrent comparator.
6
IS−1
Negative input for channel 1 overcurrent comparator.
7
VFB1
Error amplifier inverting input for channel 1.
8
COMP1
Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation. The same capacitor provides Soft−Start timing for channel 1. This pin also
disables the channel 1 output when pulled below 0.3 V.
9
COMP2
Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation and Soft−Start timing for channel 2. Channel 2 output is disabled when this pin is
pulled below 0.3 V.
10
VFB2
Error amplifier inverting input for channel 2.
11
IS−2
Negative input for channel 2 overcurrent comparator.
12
IS+2
Positive input for channel 2 overcurrent comparator.
13
ROSC
Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency.
14 VCC Input Power supply pin.
15
GATE(L)2
Low Side Synchronous FET driver pin for channel 2.
16
GATE(H)2
High Side Switch FET driver pin for channel 2.
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5

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NCP5423 arduino
NCP5422A, NCP5423
where:
IL(VALLEY) = inductor valley current.
Input Capacitor Selection
The choice and number of input capacitors is determined
by their voltage and ripple current ratings. The designer
must choose capacitors that will support the worst case input
voltage with an adequate margin. To calculate the number of
input capacitors one must first determine the RMS ripple
current through the capacitors. To this end, first calculate the
average input current to the converter:
Iin(Avg)
+
V1
·
I1
h
) V2
· Vin
·
I2
where h is the expected
efficiency (typical X 85%)
With the average input current determined, the RMS
ripple current through the input capacitor will be:
Ǹǒ Ǔ ǒ ǓIrms +
Io12
)
Ip12
3
· D1 )
Io22
)
Ip22
3
· D2−Iin2
where:
Io1,2 is the maximum DC output current for channel 1 and
2 respectively.
Ip1,2 is the peak inductor current (1/2 DIL) for channel’s
1 and 2 respectively. If the channel peak inductor current
is less than 50% of the channel output current it may be
neglected.
D1,2 is the channel duty cycle. Here it is assumed that each
channel’s duty cycle is less than 50% so that each phase
does not overlap.
Once the RMS ripple current has been determined, the
required number of input capacitor’s needed is based on the
rated RMS ripple current rating of the chosen capacitor.
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
ǒ ǓDVOUT + DIOUT
ESL
Dt
)
ESR
)
tTR
COUT
where:
DIOUT / Dt = load current slew rate;
DIOUT = load transient;
Dt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
tTR = output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula:
ESRMAX
+
DVESR
DIOUT
where:
DVESR = change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
Number
of
capacitors
+
ESRCAP
ESRMAX
where:
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet).
ESRMAX = maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
DVESR + DIOUT ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESLMAX
+
DVESL
DI
Dt
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
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