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Número de pieza AT89C5131A-M
Descripción 8-bit Flash Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo
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AT89C5131A-M datasheet

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AT89C5131A-M pdf
AT89C5130A/31A-M
Figure 3-2. AT89C5130A/31A-M 64-pin VQFP Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC 1
P2.3/A11 2
P2.4/A12 3
P2.5/A13 4
XTAL2
XTAL1
P2.6/A14
5
6
7
P2.7/A15 8
VDD 9
AVDD 10
UCAP 11
AVSS 12
NC 13
P3.0/RxD 14
NC 15
NC 16
VQFP64
48 NC
47 NC
46 P0.1/AD1
45 P0.2/AD2
44 RST
43 P0.3/AD3
42 VSS
41 NC
40 P0.4/AD4
39 P3.7/RD/LED3
38 P0.5/AD5
37 P0.6/AD6
36 P0.7/AD7
35 P3.6/WR/LED2
34 NC
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 3132
4337K–USB–04/08
5

5 Page

AT89C5131A-M arduino
Table 3-10. USB Signal Description
Signal
Name
D+
D-
VREF
Type Description
USB Data + signal
I/O
Set to high level under reset.
USB Data - signal
I/O
Set to low level under reset.
O
USB Reference Voltage
Connect this pin to D+ using a 1.5 kresistor to use the Detach function.
Alternate
Function
-
-
-
Table 3-11. System Signal Description
Signal
Name Type Description
Alternate
Function
AD[7:0]
Multiplexed Address/Data LSB for external access
I/O
Data LSB for Slave port access (used for 8-bit and 16-bit modes)
P0[7:0]
A[15:8] I/O Address Bus MSB for external access
P2[7:0]
Read Signal
RD I/O Read signal asserted during external data memory read operation.
Control input for slave port read access cycles.
P3.7
Write Signal
WR I/O Write signal asserted during external data memory write operation.
Control input for slave write access cycles.
P3.6
RST
Reset Input
Holding this pin low for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
O
This pin has an internal pull-up resistor which allows the device to be reset
by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-down mode returns
the chip to normal operation.
This pin is tied to 0 for at least 12 oscillator periods when an internal reset
occurs ( hardware watchdog or power monitor).
-
Address Latch Enable Output
ALE
O
The falling edge of ALE strobes the address into external latch. This signal
is active only when reading or writing external memory using MOVX
instructions.
-
PSEN
Program Strobe Enable / Hardware conditions Input for ISP
I/O Used as input under reset to detect external hardware conditions of ISP
mode.
-
External Access Enable
EA I This pin must be held low to force the device to fetch code from external
program memory starting at address 0000h.
-
Table 3-12. Power Signal Description
Signal
Name Type Description
AVSS
GND
Analog Ground
AVSS is used to supply the on-chip PLL and the USB PAD.
Alternate
Function
-
10 AT89C5130A/31A-M
4337K–USB–04/08

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