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PDF AT80C51SND1C Datasheet ( Hoja de datos )

Número de pieza AT80C51SND1C
Descripción Single-Chip Flash Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo
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AT80C51SND1C datasheet

1 Page

AT80C51SND1C pdf
Figure 4-3. AT8xC51SND1C 84-pin PLCC Package
AT8xC51SND1C
ALE
ISP
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.6/SCL
P1.7/SDA
VDD
PAVDD
FILT
PAVSS
VSS
X2
NC
X1
TST
UVDD
UVSS
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AT89C51SND1C-SR (FLASH)
74 NC
73 P4.5
72 P4.4
71 P2.2/A10
70 P2.3/A11
69 P2.4/A12
68 P2.5/A13
67 P2.6/A14
66 P2.7/A15
65 VSS
64 VDD
63 MCLK
62 MDAT
61 MCMD
60 RST
59 SCLK
58 DSEL
57 DCLK
56 DOUT
55 VSS
54 VDD
4.2 Signals
All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
Signal
Name
Type Description
Alternate
Function
P0.7:0
P1.7:0
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
I/O written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
polarized to VDD or VSS.
I/O
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
AD7:0
KIN3:0
SCL
SDA
P2.7:0
I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
A15:8
4109LS–8051–02/08
5

5 Page

AT80C51SND1C arduino
4.3 Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1)
VDD
AT8xC51SND1C
Type
Pins
Input
TST
Watchdog Output
VDD
P
Input/Output
RST
Latch Output
VSS
2 osc
periods
VDD
P1
VDD
P2
VDD
P3
N
VSS
VDD
P
N
VSS
VDD
P
N
VSS
Input/Output
P1(2)
P2(3)
P3
P4
P53:0
Input/Output
P0
MCMD
MDAT
ISP
PSEN
Output
ALE
SCLK
DCLK
DOUT
DSEL
MCLK
4109LS–8051–02/08
D+
D+
Input/Output
D-
D-
Notes:
1. For information on resistors value, input/output levels, and drive capability, refer to the
Section “DC Characteristics”, page 18.
2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing
pseudo open-drain structure.
3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
11

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