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PDF DS26519 Data sheet ( Hoja de datos )

Número de pieza DS26519
Descripción single-chip 16-port framer and line interface unit (LIU) combination
Fabricantes Maxim Integrated Products　
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No Preview Available ! DS26519 Hoja de datos, Descripción, Manual

DS26519
16-Port T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS26519 is a single-chip 16-port framer and line
interface unit (LIU) combination for T1, E1, and J1
16 Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer)
applications. Each port is independently configurable,
Independent T1, E1, or J1 Selections for Each
supporting both long-haul and short-haul lines. The
Transceiver
DS26519 is nearly software compatible with the
DS26528 and its derivatives.
Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Twisted Pair,
APPLICATIONS
110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
Routers
and 75Ω E1 Coaxial Applications
Channel Service Units (CSUs)
Hitless Protection Switching
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
T1/E1/J1
NETWORK
DS26519
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode
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Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
T1/J1/E1
Transceiver x16 BACKPLANE
TDM
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
ORDERING INFORMATION
PART
DS26519G
DS26519G+
DS26519GN
DS26519GN+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
484 HSBGA
484 HSBGA
484 HSBGA
484 HSBGA
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
+ Denotes lead-free/RoHS compliant device.
Features Continued in Section 2.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 040907

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DS26519 pdf
DS26519 16-Port T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 7-1. Block Diagram ......................................................................................................................................... 18
Figure 7-2. Detailed Block Diagram........................................................................................................................... 19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 34
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 34
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 34
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 34
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 35
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 35
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 35
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 35
Figure 9-9. Backplane Clock Generation................................................................................................................... 36
Figure 9-10. GPIO Mux Control ................................................................................................................................. 40
Figure 9-11. Device Interrupt Information Flow Diagram........................................................................................... 42
Figure 9-12. IBO Multiplexer Equivalent Circuit—4.096MHz .................................................................................... 47
Figure 9-13. IBO Multiplexer Equivalent Circuit—8.192MHz .................................................................................... 48
Figure 9-14. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................. 49
Figure 9-15. RSYNCn Input in H.100 (CT Bus) Mode............................................................................................... 56
Figure 9-16. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode ................................................................... 56
Figure 9-17. CRC-4 Recalculate Method .................................................................................................................. 80
Figure 9-18. HDLC Message Receive Example........................................................................................................ 86
Figure 9-19. HDLC Message Transmit Example....................................................................................................... 88
Figure 9-20. Network Connection—Longitudinal Protection ..................................................................................... 91
Figure 9-21. T1/J1 Transmit Pulse Templates .......................................................................................................... 94
Figure 9-22. E1 Transmit Pulse Templates ..................w.w.w...D..a.ta.S.h.e.e.t.4.U...c.o.m........................................................................... 95
Figure 9-23. Receive LIU Termination Options ......................................................................................................... 97
Figure 9-24. Typical Monitor Application ................................................................................................................... 98
Figure 9-25. HPS Block Diagram............................................................................................................................. 101
Figure 9-26. Jitter Attenuation ................................................................................................................................. 102
Figure 9-27. Loopback Diagram .............................................................................................................................. 103
Figure 9-28. Analog Loopback................................................................................................................................. 103
Figure 9-29. Local Loopback ................................................................................................................................... 104
Figure 9-30. Remote Loopback 2 ............................................................................................................................ 104
Figure 9-31. Dual Loopback .................................................................................................................................... 105
Figure 11-1. T1 Receive-Side D4 Timing ................................................................................................................ 268
Figure 11-2. T1 Receive-Side ESF Timing.............................................................................................................. 268
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 269
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 269
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 270
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 271
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 272
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit.................................................................... 272
Figure 11-9. T1 Transmit-Side D4 Timing ............................................................................................................... 273
Figure 11-10. T1 Transmit-Side ESF Timing........................................................................................................... 273
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 274
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 274
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 275
Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 276
Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 277
Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 277
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DS26519 arduino
DS26519 16-Port T1/E1/J1 Transceiver
2.5 Framer/Formatter
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats D4 and ESF per T1.403 and expanded SLC-96 support (TR-TSY-008)
E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe
Transmit-side synchronizer
Transmit midpath CRC recalculate (E1)
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters
− T1: BPV, CV, CRC-6, and framing bit errors
− E1: BPV, CV, CRC-4, E-bit, and frame alignment errors
− Timed or manual update modes
DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths
− User defined
− Digital Milliwatt
ANSI T1.403-1999 support
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors
− Three independent generators and detectors
− Patterns from 1 to 8 bits or 16 bits in length
Bit oriented code (BOC) support
Flexible signaling support
− Software or hardware based
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− Interrupt generated on change of signaling data
− Optional receive signaling freeze on loss of frame, loss of signal, or frame slip
− Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock
(LOTC), or signaling freeze condition
Automatic RAI generation to ETS 300 011 specifications
RAI-CI and AIS-CI support
Expanded access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
Ability to calculate and check CRC-6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
T1-to-E1 conversion
2.6 System Interface
Independent two-frame receive and transmit elastic stores
Independent control and clocking
Controlled slip capability with status
Minimum delay mode supported
Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz
Supports T1 to CEPT (E1) conversion
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Interleaving PCM bus operation
Hardware signaling capability
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
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