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PDF DS26504 Data sheet ( Hoja de datos )

Número de pieza DS26504
Descripción T1/E1/J1/64KCC BITS Element
Fabricantes Maxim Integrated Products　
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! DS26504 Hoja de datos, Descripción, Manual

DS26504
T1/E1/J1/64KCC BITS Element
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26504 is a building-integrated timing-supply
(BITS) clock-recovery element. It also functions as a
basic T1/E1 transceiver. The receiver portion can
recover a clock from T1, E1, 64kHz composite clock
(64KCC), and 6312kHz synchronization timing
interfaces. In T1 and E1 modes, the Synchronization
Status Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1, or
64KCC synchronization interfaces as well as source
the SSM in T1 and E1 modes. The DS26504 can
translate between any of the supported inbound
synchronization clock rates to any supported
outbound rate. The DS26504 can also accept an 8kHz
as well as a 19.44MHz reference clock. A separate
output is provided to source a 6312kHz clock. The
device is controlled through a parallel, serial, or
hardware controller port.
§ Transmit and Receive T1 BOC SSM Messages
with Receive Message Change of State and
Validation Indication
§ Transmit and Receive E1 Sa(n) Bit SSM
Messages with Receive Message Change of State
Indication
§ Crystal-Less Jitter Attenuator with Bypass Mode
for T1 and E1 Operation
§ Fully Independent Transmit and Receive
Functionality
§ Internal Software-Selectable Receive and
Transmit Side Termination for
75Ω/100Ω/110Ω/120Ω/133Ω
§ Monitor Mode for Bridging Applications
§ Accepts 16.384MHz, 12.8MHz, 8.192MHz,
4.096MHz, 2.048MHz, or 1.544MHz Master
Clock
§ 64kHz, 8kHz, and 400Hz Outputs in Composite
Clock Mode
APPLICATIONS
§ 8-Bitwww.DataSheet4U.com Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
BITS Timing
§ Serial (SPI) Control Port and Hardware Control
Rate Conversion
Mode
§ Provides LOS, AIS, and LOF Indications through
FEATURES
§ Accepts 8kHz and 19.44MHz References in
Addition to T1, E1, and 64kHz Composite Clock
§ GR378 Composite Clock Compliant
§ G.703 2048kHz Synchronization Interface
Compliant
§ G.703 64kHz Option A & B Centralized Clock
Synchronization Interface Compliant
Hardware Output Pins
§ Fast Transmitter Output Disable through Device
Pin for Protection Switching
§ IEEE 1149.1 JTAG Boundary Scan
§ 3.3V Supply with 5V Tolerant Inputs and
Outputs
§ Pin and Software Compatible with the DS26502
and DS26503
§ G.703 64kHz Japanese Composite Clock
Synchronization Interface Compliant
§ G.703 6312kHz Japanese Synchronization
ORDERING INFORMATION
Interface Compliant
§ Interfaces to Standard T1/J1 (1.544MHz) and E1
(2.048MHz)
PART
DS26504L
TEMP RANGE PIN-PACKAGE
0°C to +70°C 64 LQFP
§ Interface to CMI-Coded T1/J1 and E1
DS26504LN -40°C to +85°C 64 LQFP
§ T1/E1 Transmit Payload Clock Output
§ Short- and Long-Haul Line Interface
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 070105

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DS26504 pdf
DS26504 T1/E1/J1/64KCC BITS Element
LIST OF FIGURES
Figure 3-1. Block Diagram ......................................................................................................................................... 11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ......................................................................................... 12
Figure 3-3. Transmit PLL Clock Mux Diagram .......................................................................................................... 12
Figure 3-4. Master Clock PLL Diagram ..................................................................................................................... 13
Figure 13-1. Basic Network Connection .................................................................................................................... 79
Figure 13-2. Typical Monitor Application ................................................................................................................... 81
Figure 13-3. CMI Coding ........................................................................................................................................... 83
Figure 13-4. Basic Interface....................................................................................................................................... 92
Figure 13-5. Protected Interface Using Internal Receive Termination ...................................................................... 93
Figure 13-6. E1 Transmit Pulse Template ................................................................................................................. 95
Figure 13-7. T1 Transmit Pulse Template ................................................................................................................. 95
Figure 13-8. Jitter Tolerance (T1 Mode) .................................................................................................................... 96
Figure 13-9. Jitter Tolerance (E1 Mode).................................................................................................................... 96
Figure 13-10. Jitter Attenuation (T1 Mode)................................................................................................................ 97
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................................... 97
Figure 15-1. 64kHz Composite Clock Mode Signal Format ...................................................................................... 99
Figure 17-1. JTAG Functional Block Diagram ......................................................................................................... 102
Figure 17-2. TAP Controller State Diagram............................................................................................................. 105
Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................................... 110
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................................... 110
Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................................... 110
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................................... 111
Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................................... 111
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................................... 111
Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................................... 112
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................................... 112
Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) ............................................................................... 116
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0w]w=w.D0ata0Sh)ee.t.4.U...co.m.......................................................................... 116
Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00)................................................................................... 117
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) ................................................................................ 119
Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01) ................................................................................ 119
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) ......................................................................... 120
Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01) ......................................................................... 120
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10.................................................................... 122
Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10.................................................................... 122
Figure 20-10. Receive Timing—T1, E1, 64KCC Mode............................................................................................ 124
Figure 20-11. Transmit Timing—T1, E1, 64KCC Mode........................................................................................... 126
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DS26504 arduino
DS26504 T1/E1/J1/64KCC BITS Element
3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
MCLK
MASTER CLOCK
DS26504
JA CLOCK
RTIP
RRING
RLOS
RAIS
TNEGO
TPOSO
TTIP
TRING
THZE
RLRILXUIXU
TX
LIU
CLOCK
+ DATA
- DATA
L
O
C
A
L
L
O
O
P
B
A
C
K
M
U
X
JA
ENABLED
AND IN RX
PATH
R
E
M
O
T
E
JITTER
ATTENUATOR
L
CAN BE
O
ASSIGNED TO
RECEIVE OR
O
TRANSMIT PATH P
OR DISABLED B
PLL
CLOCK
MUX
A
C
JA
ENABLED
AND IN TX
PATH
K
TX CLOCK
M
www.DataSheet4U.com
U
X
+ DATA
- DATA
T1/E1 SSM
FRAMER
64KCC
DECODER
T1/E1 SSM
FORMATTER
64KCC
CODER
TCLKO
JTAJGTAPGOPROTRT
PARALLEL/SERIAL CPU I/F
HARDWARE CONTROLLER
JTMS JTRST JTCLK JTDI JTDO
BIS1 BIS0
PARALLEL,
SERIAL, OR
HARDWARE
CONTROLLER
RCLK
LOF_CCE
RSER
RS_8K
400HZ
TCLK
PLL_OUT
TSER
TS_8K_4
TSTRST
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