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Número de pieza | DS26503 | |
Descripción | T1/E1/J1 BITS Element | |
Fabricantes | Dallas Semiconducotr | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de DS26503 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! DS26503
T1/E1/J1 BITS Element
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS26503 is a building-integrated timing-
§ G.703 2048kHz Synchronization Interface
supply (BITS) clock-recovery element. The
Compliant
receiver portion can recover a clock from T1,
§ G.703 6312kHz Japanese Synchronization
E1, and 6312kHz synchronization timing
Interface Compliant
interfaces. In T1 and E1 modes, the
§ Interfaces to Standard T1/J1 (1.544MHz) and
Synchronization Status Message (SSM) can also
E1 (2.048MHz)
be recovered. The transmit portion can directly
§ Interface to CMI-Coded T1/J1 and E1
interface to T1 or E1 interfaces as well as source
§ Short- and Long-Haul Line Interface
the SSM in T1 and E1 modes. The DS26503 can
§ Transmit and Receive T1 and E1 SSM
translate between any of the supported inbound
Messages with Message Validation
synchronization clock rates to any supported
§ Crystal-Less Jitter Attenuator with Bypass
outbound rate. A separate output is provided to
Mode
source a 6312kHz clock. The device is
§ Fully Independent Transmit and Receive
controlled through a parallel, serial, or hardware
Functionality
controller port.
§ Internal Software-Selectable Receive- and
Transmit-Side Termination for
www.DataSheet4U.com 75Ω/100Ω/110Ω/120Ω
APPLICATIONS
§ Monitor Mode for Bridging Applications
BITS Timing
Rate Conversion
Basic Transceiver
§ Accepts 16.384MHz, 8.192MHz, 4.096MHz,
2.048MHz, or 1.544MHz (T1 Only) Master
Clock
§ 8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
§ Serial (SPI) Control Port
§ Hardware Control Mode
§ Provides LOS, AIS, and LOF Indications
DS26503L 0°C to +70°C 64 LQFP
Through Hardware Output Pins
DS26503LN -40°C to +85°C 64 LQFP
§ Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
§ IEEE 1149.1 JTAG Boundary Scan
§ 3.3V Supply with 5V-Tolerant Inputs and
Outputs
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 070904
1 page DS26503 T1/E1/J1 BITS Element
LIST OF FIGURES
Figure 3-1. Block Diagram ..................................................................................................................... 12
Figure 3-2. Loopback Mux Diagram....................................................................................................... 13
Figure 3-3. Transmit PLL Clock Mux Diagram ....................................................................................... 13
Figure 3-4. Master Clock PLL Diagram.................................................................................................. 14
Figure 13-1. Basic Network Connection................................................................................................. 77
Figure 13-2. Typical Monitor Application................................................................................................ 79
Figure 13-3. CMI Coding ....................................................................................................................... 81
Figure 13-4. Basic Interface................................................................................................................... 90
Figure 13-5. Protected Interface Using Internal Receive Termination .................................................... 91
Figure 13-6. E1 Transmit Pulse Template ............................................................................................. 93
Figure 13-7. T1 Transmit Pulse Template.............................................................................................. 93
Figure 13-8. Jitter Tolerance (T1 Mode) ................................................................................................ 94
Figure 13-9. Jitter Tolerance (E1 Mode) ................................................................................................ 94
Figure 13-10. Jitter Attenuation (T1 Mode) ............................................................................................ 95
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................ 95
Figure 16-1. JTAG Functional Block Diagram........................................................................................ 98
Figure 16-2. TAP Controller State Diagram ......................................................................................... 101
Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................. 106
Figure 17-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................. 106
Figure 17-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................. 106
Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................. 107
Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................. 107
Figure 17-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................. 107
Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................. 108
Figure 17-8. SPI Serial Port Access, Write Mode, CPOL = 1,www.DataSheet4U.com CPHA = 1 ............................................. 108
Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)............................................................. 112
Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00).............................................................. 112
Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ................................................................ 113
Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ................................................. 118
Figure 19-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ................................................. 118
Figure 19-10. Receive Timing, T1/E1 .................................................................................................. 120
Figure 19-11. Transmit Timing, T1/E1 ................................................................................................. 122
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5 Page DS26503 T1/E1/J1 BITS Element
Table 2-3. E1-Related Telecommunications Specifications (continued)
(ETSI) “Business Telecommunications (BT); Open Network Provision (ONP) technical requirements;
2048lkbps digital unstructured leased lines (D2048U) attachment requirements for terminal equipment
interface”
(ETSI) “Business Telecommunications (BTC); 2048kbps digital structured leased lines (D2048S);
Attachment requirements for terminal equipment interface”
(ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44,736kbps Hierarchical
Levels”
(ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame
Structures Defined in Recommendation G.704”
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11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet DS26503.PDF ] |
Número de pieza | Descripción | Fabricantes |
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