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PDF DS26502 Data sheet ( Hoja de datos )
| Número de pieza | DS26502 | |
| Descripción | T1/E1/J1/64KCC BITS Element | |
| Fabricantes | Maxim Integrated Products | |
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DS26502
T1/E1/J1/64KCC BITS Element
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS26502 is a building-integrated timing-
§ G.703 2048kHz Synchronization Interface
supply (BITS) clock-recovery element. It also
Compliant
functions as a basic T1/E1 transceiver. The
§ G.703 64kHz Centralized (Option A) and
receiver portion can recover a clock from T1,
Codirectional Timing Interface Compliant
E1, 64kHz composite clock (64KCC), and
§ G.703 Appendix II 64kHz and 6312kHz
6312kHz synchronization timing interfaces. In
Japanese Synchronization Interface
T1 and E1 modes, the Synchronization Status
Compliant
Message (SSM) can also be recovered. The
§ Interfaces to Standard T1/J1 (1.544MHz) and
transmit portion can directly interface to T1, E1,
E1 (2.048MHz)
or 64KCC synchronization interfaces as well as
§ Interface to CMI-Coded T1/J1 and E1
source the SSM in T1 and E1 modes. The
§ Short- and Long-Haul Line Interface
DS26502 can translate between any of the
§ Transmit and Receive T1 and E1 SSM
supported inbound synchronization clock rates to
Messages with Message Validation
any supported outbound rate. A separate output
§ T1/E1 Jitter Attenuator with Bypass Mode
is provided to source a 6312kHz clock. The
§ Fully Independent Transmit and Receive
device is controlled through a parallel, serial, or
Functionality
hardware controller port.
§ Internalwww.DataSheet4U.com Software-Selectable Receive- and
Transmit-Side Termination for
75Ω/100Ω/110Ω/120Ω T1, E1, and
APPLICATIONS
Composite Clock Interfaces
BITS Timing
Rate Conversion
§ Monitor Mode for Bridging Applications
§ Accepts 16.384MHz, 8.192MHz, 4.096MHz,
or 2.048MHz Master Clock
§ 64kHz, 8kHZ, and 400Hz Outputs in
ORDERING INFORMATION
Composite Clock Mode
PART TEMP RANGE PIN-PACKAGE
§ 8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
DS26502L 0°C to +70°C 64 LQFP
§ Serial (SPI) Control Port
DS26502LN -40°C to +85°C 64 LQFP
§ Hardware Control Mode
§ Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
§ Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
§ IEEE 1149.1 JTAG Boundary Scan
§ 3.3V Supply with 5V-Tolerant Inputs and
Outputs
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 032405
1 page  
DS26502 T1/E1/J1/64KCC BITS Element
LIST OF FIGURES
Figure 3-1. Block Diagram ..................................................................................................................... 11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ...................................................................... 12
Figure 3-3. Transmit PLL Clock Mux Diagram ....................................................................................... 12
Figure 3-4. Master Clock PLL Diagram.................................................................................................. 13
Figure 13-1. Basic Network Connection................................................................................................. 76
Figure 13-2. Typical Monitor Application................................................................................................ 78
Figure 13-3. CMI Coding ....................................................................................................................... 80
Figure 13-4. Software-Selected Termination, Metallic Protection........................................................... 89
Figure 13-5. Software-Selected Termination, Longitudinal Protection.................................................... 90
Figure 13-6. E1 Transmit Pulse Template ............................................................................................. 91
Figure 13-7. T1 Transmit Pulse Template.............................................................................................. 91
Figure 13-8. Jitter Tolerance (T1 Mode) ................................................................................................ 92
Figure 13-9. Jitter Tolerance (E1 Mode) ................................................................................................ 92
Figure 13-10. Jitter Attenuation (T1 Mode) ............................................................................................ 93
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................ 93
Figure 15-1. 64kHz Composite Clock Mode Signal Format.................................................................... 95
Figure 17-1. JTAG Functional Block Diagram........................................................................................ 98
Figure 17-2. TAP Controller State Diagram ......................................................................................... 101
Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................. 106
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................. 106
Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................. 106
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................. 107
Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................. 107
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................. 107
Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0,www.DataSheet4U.com CPHA = 1 ............................................. 108
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................. 108
Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)............................................................. 112
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00).............................................................. 112
Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ................................................................ 113
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ................................................. 118
Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ................................................. 118
Figure 20-10. Receive Timing, T1, E1, 64KCC Mode .......................................................................... 120
Figure 20-11. Transmit Timing, T1, E1, 64KCC Mode ......................................................................... 122
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5 Page 
DS26502 T1/E1/J1/64KCC BITS Element
3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
MCLK
MASTER CLOCK
DS26502
JA CLOCK
RTIP
RRING
RLOS
RAIS
TNEGO
TPOSO
TTIP
TRING
THZE
RLIRLXUIXU
TX
LIU
CLOCK
+ DATA
- DATA
L
O
C
A
L
L
O
O
P
B
A
C
K
M
U
X
JA
ENABLED
AND IN RX
PATH
R
E
M
O
T
E
JITTER
ATTENUATOR
L
CAN BE
O
ASSIGNED TO
RECEIVE OR
O
TRANSMIT PATH P
OR DISABLED B
TX PLL
CLOCK
MUX
A
C
K TX CLOCK
JA
ENABLED
AND IN TX
PATH
M www.DataSheet4U.com + DATA
U - DATA
X
T1/E1 SSM
FRAMER
64KCC
DECODER
T1/E1 SSM
FORMATTER
64KCC
CODER
TCLKO
JTAJGTAPGOPROTRT
PARALLEL/SERIAL CPU I/F
HARDWARE CONTROLLER
JTMS JTRST JTCLK JTDI JTDO
BIS1 BIS0
PARALLEL,
SERIAL, OR
HARDWARE
CONTROLLER
RCLK
LOF_CCE
RSER
RS_8K
400HZ
TCLK
PLL_OUT
TSER
TS_8K_4
TSTRST
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS26502.PDF ] | |
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