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PDF WM8581 Data sheet ( Hoja de datos )
| Número de pieza | WM8581 | |
| Descripción | Multichannel CODEC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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WM8581
Multichannel CODEC with S/PDIF Transceiver
DESCRIPTION
FEATURES
The WM8581 is a multi-channel audio CODEC with S/PDIF
transceiver. The WM8581 is ideal for DVD and surround
• Multi-channel CODEC with 4 Stereo DACs and 1 Stereo
ADC
sound processing applications for home hi-fi, automotive
and other audiovisual equipment.
• Integrated S/PDIF / IEC-60958-3 transceiver
• Audio Performance
Integrated into the device is a stereo 24-bit multi-bit sigma
− 103dB SNR (‘A’ weighted @ 48kHz) DAC
delta ADC with support for digital audio output word lengths
from 16-bit to 32-bit, and sampling rates from 8kHz to
192kHz.
− -90dB THD (48kHz) DAC
− 100dB SNR (‘A’ weighted @ 48kHz) ADC
− -87dB THD (48kHz) ADC
Also included are four stereo 24-bit multi-bit sigma delta
DACs, each with a dedicated oversampling digital
interpolation filter. Digital audio input word lengths from 16-
bits to 32-bits and sampling rates from 8kHz to 192kHz are
supported. Each DAC channel has independent digital
volume and mute control.
Two independent audio data interfaces support I2S, Left
Justified, Right Justified and DSP digital audio formats.
Each audio interface can operate in either Master Mode or
Slave Mode.
• DAC Sampling Frequency: 8kHz – 192kHz
• ADC Sampling Frequency: 8kHz – 192kHz
• Independent ADC and DAC Sample Rates
• 2 and 3-Wire Serial Control Interface with readback, or
Hardware Control Interface
• GPO pins allow visibility of user selected status flags
• Programmable Audio Data Interface Modes
− I2S, Left, Right Justified or DSP
− 16/20/24/32 bit Word Lengths
The S/PDIF transceiver is IEC-60958-3 compatible
supports frame rates from 32k/s to 96k/s. It has
multiplexed inputs and one output. Status and
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DAC outputs with independent
or Slave Audio Data Interfaces
monitoring is built-in and results can reported over the serial
• Flexible Digital Interface Routing with Clock Selection
interface or via GPO pins. S/PDIF Channel Block
Control
configuration is also supported.
The device has two PLLs that can be configured
independently to generate two system clocks for internal or
• 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply
Operation
• 48-lead TQFP Package
external use.
Device control and setup is via a 2-wire or 3-wire (SPI
compatible) serial interface. The serial interface provides
access to all features including channel selection, volume
controls, mutes, de-emphasis, S/PDIF control/status, and
power management facilities. Alternatively, the device has a
Hardware Control Mode where device features can be
enabled/disabled using selected pins.
APPLICATIONS
• Digital TV
• DVD Players and Receivers
• Surround Sound AV Processors and Hi-Fi systems
• Automotive Audio
The device is available in a 48-lead TQFP package.
WOLFSON MICROELECTRONICS plc
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Production Data, April 2007, Rev 4.0
Copyright ©2007 Wolfson Microelectronics plc
1 page  
Production Data
PIN DESCRIPTION
PIN NAME
1 VOUT4L
2 VOUT4R
3 PGND
4 PVDD
5 XTI
6 XTO
7 MFP7
8 MFP6
9 SPDIFOP
10 MFP5
11 MFP4
12 MFP3
13 SPDIFIN1
14 CLKOUT
15 DVDD
16 DGND
17 MUTE
18 DIN1
19 DIN2
20 DIN3
21 DIN4
22 PAIFRX_LRCLK
23 PAIFRX_BCLK
24 MCLK
25 DOUT
26 PAIFTX_LRCLK
27 MFP1
28 MFP2
29 HWMODE
30 SWMODE
31 SDO
32 SDIN
33 SCLK
34 CSB
35 AINR
36 AINL
37 ADCREFP
38 VMID
39 AGND
40 AVDD
41 VOUT1L
42 VOUT1R
43 VOUT2L
44 VOUT2R
45 VREFP
46 VREFN
WM8581
TYPE
Analogue Output
Analogue Output
Supply
Supply
Digital Input
Digital Output
Digital Input/Output
Digital Input/Output
Digital Output
Digital Input/Output
Digital Input/Output
Digital Input/Output
Digital Input
Digital Output
Supply
Supply
Digital Input/Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input/Output
Digital Input/Output
Digital Input/Output
Digital Output
Digital Input/Output
Digital Input/Output
Digital Input/Output
Digital Input
Digital Input/Output
Digital Output
Digital Input/Output
Digital Input
Digital Input
Analogue Input
Analogue Input
Analogue Output
Analogue Output
Supply
Supply
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Analogue Input
Analogue Input
DESCRIPTION
DAC channel 4 left output
DAC channel 4 right output
PLL ground
PLL positive supply
Crystal or CMOS clock input
Crystal output
Multi-Function Pin (MFP) 7. See Table 1 for details of all MFP pins.
Multi-Function Pin (MFP) 6. See Table 1 for details of all MFP pins.
S/PDIF transmitter output
Multi-Function Pin (MFP) 5. See Table 1 for details of all MFP pins.
Multi-Function Pin (MFP) 4. See Table 1 for details of all MFP pins.
Multi-Function Pin (MFP) 3. See Table 1 for details of all MFP pins.
S/PDIF Receiver Input 1
PLL or crystal oscillator clock output
Digital positive supply
Digital ground
DAC mute-all input/ All-DAC Infinite Zero Detect (IZD) flag output
Primary Audio Interface (PAIF) receiver data input 1
Primary Audio Interface (PAIF) receiver data input 2
Primary Audio Interface (PAIF) receiver data input 3
Primary Audio Interface (PAIF) receiver data input 4
Primary Audio Interface (PAIF) receiver left/right word clock
Primary Audio Interface (PAIF) receiver bit clock
System Master clock; 256, 384, 512, 768, 1024 or 1152 fs
Primary Audio Interface (PAIF) transmitter data output
Primary audio interface transmitter left/right word clock
Multi-Function Pin (MFP) 1. See Table 1 for details of all MFP pins.
Multi-Function Pin (MFP) 2. See Table 1 for details of all MFP pins.
Configures control to be either Software Mode or Hardware Mode
Configures software interface to be either 2-wire or 3-wire. See note 2.
3-wire control interface data output. See note 3.
Control interface data input (and output under 2-wire control)
Control interface clock
3-wire control interface latch signal / device address selection
ADC Right Channel Input
ADC Left Channel Input
ADC reference buffer decoupling pin; 10uF external decoupling
Midrail divider decoupling pin; 10uF external decoupling
Analogue ground
Analogue positive supply
DAC channel 1 left output
DAC channel 1 right output
DAC channel 2 left output
DAC channel 2 right output
DAC and ADC positive reference
DAC and ADC ground reference
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PD Rev 4.0 April 2007
5
5 Page 
Production Data
WM8581
Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz,
24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
1kHz, 0dB Full Scale @
fs = 96kHz
-87
dB
1kHz, 0dB Full Scale @
fs = 192kHz
-84
dB
DAC Channel separation
100 dB
Mute Attenuation
1kHz Input, 0dB gain
100
dB
Output Offset Error
2 mV
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PD Rev 4.0 April 2007
11
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| PDF Descargar | [ Datasheet WM8581.PDF ] | |
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