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PDF NTHD5903 Data sheet ( Hoja de datos )

Número de pieza NTHD5903
Descripción Power MOSFET ( Transistor )
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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NTHD5903
Power MOSFET
−20 V, −3.0 A, Dual P−Channel ChipFETE
Features
Low RDS(on) for Higher Efficiency
Logic Level Gate Drive
Miniature ChipFET Surface Mount Package Saves Board Space
Pb−Free Package is Available
Applications
Power Management in Portable and Battery−Powered Products;
i.e., Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Steady
Symbol 5 secs State
Unit
Drain−Source Voltage
Gate−Source Voltage
Continuous Drain Current
(TJ = 150°C) (Note 1)
TA = 25°C
TA = 85°C
Pulsed Drain Current
Continuous Source Current
(Diode Conduction) (Note 1)
VDS
VGS
ID
IDM
IS
−20 V
"12
V
Awww.DataSheet4U.com
"3.0
"2.2
"2.2
"1.6
"10
A
−3.0 −2.2 A
Maximum Power Dissipation
(Note 1)
TA = 25°C
TA = 85°C
Operating Junction and Storage
Temperature Range
PD
TJ, Tstg
2.1 1.1
1.1 0.6
−55 to +150
W
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
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V(BR)DSS
−20 V
RDS(on) TYP
130 mW @ −4.5 V
215 mW @ −2.5 V
S1
ID MAX
−3.0 A
S2
G1 G2
D1
P−Channel MOSFET
D2
P−Channel MOSFET
ChipFET
CASE 1206A
STYLE 2
PIN
CONNECTIONS
MARKING
DIAGRAM
D1 8
D1 7
D2 6
D2 5
1 S1
2 G1
3 S2
4 G2
1
2
3
4
8
7
6
5
A7 = Specific Device Code
M = Month Code
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
NTHD5903T1
ChipFET 3000/Tape & Reel
NTHD5903T1G ChipFET 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 4
1
Publication Order Number:
NTHD5903/D

1 page




NTHD5903 pdf
0.457
0.018
2.032
0.08
NTHD5903
SOLDERING FOOTPRINT*
0.635
0.025
0.635
0.025
2.032
0.08
1.092
0.043
0.66
0.026
0.711
0.028
Figure 12. Basic
0.457
0.018
0.178
0.007
0.66
0.026
0.254
0.010
SCALE 20:1
ǒ mm Ǔ
inches
Figure 13. Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
http://onsemi.com
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