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PDF CAT24WC164 Data sheet ( Hoja de datos )

Número de pieza CAT24WC164
Descripción 16K-Bit Serial EEPROM
Fabricantes Catalyst Semiconductor 
Logotipo Catalyst Semiconductor Logotipo



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No Preview Available ! CAT24WC164 Hoja de datos, Descripción, Manual

CAT24WC164
ALOGEN FR
16K-Bit Serial EEPROM, Cascadable
LEA D F REETM
FEATURES
I Self-timed write cycle with auto-clear
I 400 kHz I2C bus compatible*
I 1,000,000 program/erase cycles
I 1.8 to 5.5 volt operation
I 100 year data retention
I Low power CMOS technology
I Write protect feature
- Entire array protected when WP at V
IH
I Page write buffer
rtDESCRIPTION
aThe CAT24WC164 is a16K-bit, cascadable Serial CMOS
EEPROM internally organized as 2048 words of 8 bits
each. Catalyst’s advanced CMOS technology substan-
Ptially reduces device power requirements. The
I 8-pin DIP, 8-pin SOIC, 8-pin MSOP or
8 pin TSSOP
(Also available in "Green" packages)
I Industrial, automotive and
extended temperature ranges
CAT24WC164 features a 16-byte page write buffer. The
device operates via the I2C bus serial interface, has a
special write protection feature, and is available in 8-pin
DIP, 8-pin SOIC, 8-pin TSSOP and 8-lead MSOP.
dPIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L)
SOIC Package (J, W)
EXTERNAL LOAD
eA0
A1
uA2
tinVSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WPwww.DataSheet4U.com
6 SCL
5 SDA
VCC
5020 FHD F01
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
MSOP Package (R, Z)
TSSOP Package (U, Y)
nA0
A1
oA2
VSS
1
2
3
4
8 VCC
A0
7 TEST A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8
7
6
5
SDA
VCC
WP
SCL
SDA WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
iscPIN FUNCTIONS
Pin Name
Function
DA0, A1, A2 Device Address Inputs
DATA IN STORAGE
SDA
Serial Data/Address
HIGH VOLTAGE/
TIMING CONTROL
SCL Serial Clock
WP Write Protect
SCL STATE COUNTERS
VCC +1.8V to +5.5V Power Supply
VSS Ground
A0 SLAVE
A1 ADDRESS
A2 COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1026, Rev. J

1 page




CAT24WC164 pdf
CAT24WC164
address pins (A0, A1and A2) can be left floating or DEVICE ADDRESSING
connected to VSS.
The CAT24WC164 can be made compatible with the
CAT24WC16 by tying A2, A1 and A0 to VSS or by
leaving A2, A1 and A0 float.
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
WP: Write Protect
If the WP pin is tied to VCC the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to VSS or left floating normal read/write
operations are allowed to the device.
I2C BUS PROTOCOL
rtThe following defines the features of the I2C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
a(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
Pin the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
dThe START Condition precedes all commands to the
edevice, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC164 monitor the
SDA and SCL lines and will not respond until this
ucondition is met.
tinSTOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Fig. 5). The next three significant bits (A2, A1, A0) are
the device address bits and define which device or which
part of the device the Master is accessing (The A1 bit
must be the compliment of the A1 input pin signal). Up
to eight CAT24WC164 devices may be individually
addressed by the system. The next three bits are used
as the three most significant bits of the data word
address. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC164 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC164 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowl-
edging device pulls down the SDA line during the ninth
clock cycle, signaling that it received the 8 bits of data.
The CAT24WC164 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
onFigure 4. Acknowledge Timing
cSCL FROM
is MASTER
D DATA OUTPUT
1
89
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5 Doc. No. 1026, Rev. J

5 Page





CAT24WC164 arduino
8-LEAD TSSOP (U,Y)
CAT24WC164
Discontinued Part
11 Doc. No. 1026, Rev. J

11 Page







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