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PDF CAT24FC66 Data sheet ( Hoja de datos )
| Número de pieza | CAT24FC66 | |
| Descripción | (CAT24FC65 / CAT24FC66) 64K-Bit I2C Serial CMOS EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24FC65, CAT24FC66
64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection
FEATURES
I Fast mode I2C bus compatible*
I Max clock frequency:
- 400KHz for VCC=2.5V to 5.5V
I Schmitt trigger filtered inputs for
noise suppression
I Low power CMOS technology
I 64-byte page write buffer
I Self-timed write cycle with auto-clear
I Industrial and automotive temperature ranges
I 5 ms max write cycle time
I Write protect feature
– Bottom 1/4 array protected when WP at V
IH
(CAT24FC65)
– Top 1/4 array protected when WP at VIH
(CAT24FC66)
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
The CAT24FC65/66 is a 64k-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements.
The CAT24FC65/66 features a 64-byte page write
buffer. The device operates via the I2C bus serial
interface and is available in 8-pin DIP, SOIC, TSSOP
and TDFN packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package
(J, W, K, X, GW, GX)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
TDFN Package (RD2, ZD2)
EXTERNAL LOAD
www.DataSheet4U.com
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
TSSOP Package (U, Y, GY)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
Pin Name
Function
A0, A1, A2 Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +2.5V to +5.5V Power Supply
VSS Ground
NC No Connect
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
EEPROM
128 128X512
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1047, Rev. H
1 page  
CAT24FC65/66
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC65/66 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC65/66 uses the next three
bits as address bits. The address bits A2, A1 and A0
allow as many as eight devices on the same bus. These
bits must compare to their hardwired input pins. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC65/66 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC65/66 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24FC65/66 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiving
each 8-bit byte.
When the CAT24FC65/66 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24FC65/66 will continue to
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1047, Rev. H
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT24FC66.PDF ] | |
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