|
|
PDF CAT24FC17 Data sheet ( Hoja de datos )
| Número de pieza | CAT24FC17 | |
| Descripción | 16-kb I2C Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CAT24FC17 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
CAT24FC17
16-kb I2C Serial EEPROM
FEATURES
I 400 kHz (2.5 V) I2C bus compatible
I 2.5 to 5.5 volt operation
I Low power CMOS technology
I 16-byte page write buffer
I Industrial and extended temperature ranges
I Self-timed write cycle with auto-clear
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin MSOP
and TDFN packages
- “Green” package option available
I 256 x 8 Memory organization
I Hardware write protect
- Top 1/2 array protected when WP at VIH
DESCRIPTION
The CAT24FC17 is a 16-kb Serial CMOS EEPROM
internally organized as 2048 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC17
features a 16-byte page write buffer. The device operates
via the I2C bus serial interface has a special write
protection feature and is available in 8-pin DIP, SOIC,
TSSOP, MSOP and TDFN packages.
PIN CONFIGURATION
BLOCK DIAGRAM
EXTERNAL LOAD
DIP Package (P, L, GL)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J, W, GW)
NC
NC
NC
VSS
1
2
3
4
www.DataSheet4U.com
8 VCC
7 WP
6 SCL
5 SDA
VCC
VSS
SDA
DOUT
ACK
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
TSSOP Package (U, Y, GY)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
MSOP Package (R, Z, GZ)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
TDFN Package
(RD4, ZD4, GD4)
VCC 1
WP 2
SCL 3
SDA 4
8 NC
7 NC
6 NC
5 VSS
* Catalyst Semiconductor is licensed by Philips Corporation
to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
XDEC
E2PROM
WP CONTROL
LOGIC
DATA IN STORAGE
SCL
STATE COUNTERS
HIGH VOLTAGE/
TIMING CONTROL
PIN FUNCTIONS
Pin Name
Function
NC No Connect
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC 2.5 V to 5.5 V Power Supply
VSS Ground
1 Doc. No. 1077, Rev. F
1 page  
CAT24FC17
I2C BUS PROTOCOL
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC17 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC17 (see Fig. 5). The next three
significant bits (A10, A9, A8) are the memory array
address bits. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC17 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC17 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24FC17 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT24FC17 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC17 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Slave Address Bits
ACKNOWLEDGE
1 0 1 0 A10 A9 A8 R/W Normal Read and Write
DEVICE ADDRESS
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1077, Rev. F
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT24FC17.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CAT24FC16 | 16-kb I2C Serial EEPROM | Catalyst Semiconductor |
| CAT24FC17 | 16-kb I2C Serial EEPROM | Catalyst Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |