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PDF UC2842B Data sheet ( Hoja de datos )
| Número de pieza | UC2842B | |
| Descripción | (UC2842B - UC2845B) HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UC2842B (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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UC2842B/3B/4B/5B
® UC3842B/3B/4B/5B
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
. TRIMMED OSCILLATOR FOR PRECISE FRE-
QUENCY CONTROL
. OSCILLATOR FREQUENCY GUARANTEED
AT 250kHz
. CURRENT MODE OPERATION TO 500kHz
. AUTOMATIC FEED FORWARD COMPENSA-
TION
. LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
. INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
. HIGH CURRENT TOTEM POLE OUTPUT
. UNDERVOLTAGE LOCKOUT WITH HYSTER-
ESIS
. LOW START-UP AND OPERATING CURRENT
Minidip
SO8
comparatorwhich alsoprovidescurrent limit control,
and a totem pole output stage designed to source
or sink high peakcurrent. The outputstage, suitable
for driving N-Channel MOSFETs, is low in the off-
state.
DESCRIPTION
Differences between members of this family are the
under-voltagelockout thresholds and maximum duty
TheUC384xB family ofcontrolICs providesthe nec- cycle ranges. The UC3842B and UC3844B have
essary features to implement off-line or DC to DC UVLO thresholds of 16V (on) and 10V (off), ideally
fixed frequency current mode control schemes wwwwit.DhataSheet4Us.cuomitedoff-lineapplicationsThecorrespondingthresh-
a minimal external parts count. Internally imple- oldsforthe UC3843BandUC3845Bare8.5 V and7.9
mented circuits include a trimmed oscillator for pre- V. The UC3842B and UC3843B can operate to duty
cise DUTY CYCLE CONTROL under voltage lock- cycles approaching 100%. A range of the zero to <
outfeaturingstart-up current less than0.5mA,a pre- 50 % is obtained by the UC3844B and UC3845B by
cision reference trimmed for accuracy at the error the addition of an internal toggle flip flopwhich blanks
amp input, logicto insure latched operation,a PWM the output off every otherclock cycle.
BLOCK DIAGRAM (toggle flip flop used only in UC3844B and UC3845B)
7
Vi
5
GROUND
4
RT/CT
VFB
COMP
CURRENT
SENSE
2
1
3
34V UVLO
S/R
5V
REF
2.50V
OSC
VREF GOOD
LOGIC
INTERNAL
BIAS
T
8 VREF
5V 50mA
6
OUTPUT
ERROR AMP.
+
-
2R
R
S
R
1V
CURRENT
SENSE
COMPARATOR
PWM
LATCH
UC3842B
D95IN331
March 1999
1/15
1 page  
Figure 1: Open Loop Test Circuit.
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
4.7KΩ
ERROR AMP.
ADJUST
4.7KΩ
2N2222
100KΩ
1KΩ
ISENSE
ADJUST
5KΩ
RT
COMP
VFB
ISENSE
RT/CT
VREF
8
17
2
UC2842B
3
6
4
5
0.1µF
Vi
OUTPUT
0.1µF
GROUND
D95IN343
CT
A
1W
1KΩ
VREF
Vi
OUTPUT
GROUND
High peak currents associatedwith capacitive loads
necessitate careful grounding techniques. Timing
and bypass capacitors should be connected close
to pin 5 in a single point ground. The transistor and
5 KΩ potentiometerareusedto samplethe oscillator
waveform and apply an adjustable ramp to pin 3.
Figure 2: Timing Resistor vs. Oscillator Fre-
quency
RT
(KΩ)
50
20
10
CT=5nF
D95IN333
C
T=200pF
C
C T=500pF
T =1nF
C
T =100pF
5
2
Vi=15V
TA=25°C
1
0.8
10K
20K
CT=10nF
30K 50K
CT=2nF
100K
200K 300K 500K
fOSC(KHz)
Figure 3: Output Dead-Time vs. Oscillator Fre-
quency
D95IN334
%
50
30
20
10
5
3
2
1
10K
CT=1nF
CT=500pF
CT=200pF
CT=2nF
CT=5nF
CT=10nF
CT=100pF
20K 30K 50K
100K
Vi=15V
TA=25°C
200K 300K 500K fOSC(KHz)
5/15
5 Page 
Figure 22: External Clock Synchronization.
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
EXTERNAL
SYNC INPUT 0.01µF
VREF
8
RT
4
CT
2
47Ω
1
R
R
+
+
-
EA
BIAS
OSC
2R
R
5
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground
D95IN352
Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.
VREF
RA
8
RB 5K
6
+
5
-
5K
+
2
-
C 5K
1
4
R
Q
S
NE555
1.44
f=
(RA + 2RB)C
Dmax =
RB
RA + 2RB
3
7
8
R
BIAS
R
4
OSC
+
+
2
-
EA
1
2R
R
5
TO ADDITIONAL
UCX84XAs
D95IN353
11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet UC2842B.PDF ] | |
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